Catching Critical Defects In TSVs And Stacked Chips


Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect capture rate and distinguishing between yield-killing and false positives. New methods for interconnecting devices using through-silicon vias (TSVs) and hybrid bonding in stac... » read more

Increasing Semiconductor Device Reliability Requires Adding More Wafer Inspection


Some industry sectors such as automotive and medical continue to push for higher and higher reliability levels; however, many fabs are having difficulties achieving them. Current inspection regimes still allow too many defects to pass through and escape to the field – primarily because of time and expense issues. Too much wafer is still left uninspected One fundamental problem is the amount... » read more

How Advanced Packaging Is Reshaping Inspection


As semiconductor devices continue advancing into more sophisticated packaging schemes, traditional optical inspection technologies are brushing up against physical and computational boundaries. The growing reliance on 2.5D and 3D integration, hybrid bonding, and wafer-level processes has made it much harder to detect defects consistently and early enough to protect yields. While optical insp... » read more

E-Beam Inspection Proves Essential For Advanced Nodes


Electron-beam inspection is proving to be indispensable for finding critical defects at sub-5nm dimensions. The challenge now is how to speed up the process to make it economically palatable to fabs. E-beam inspection's notorious sensitivity-throughput tradeoff has made comprehensive defect coverage with e-beam at these advanced nodes especially problematic. For Intel’s 18A logic node (~1.... » read more

Hunting For Macro Defects


Detecting macro-defects early in the wafer processing flow is vital for yield and process improvement, and it is driving innovations in both inspection techniques and wafer test map analysis. At the wafer level, a macro-defect can affect more than one die, and in some cases large regions of a wafer. Finding macro defects can indicate a significant issue with a process module, a particular fi... » read more

Need For KGD Drives Singulated Die Screening


The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly higher than with a single die. Better methods for inspecting and testing these devices are already starting to roll out. High-throughput infrared inspection is capable of catching more sub-surface d... » read more

Review of Automatic EM Image Algorithms for Semiconductor Defect Inspection (KU Leuven, Imec)


A new technical paper titled "Electron Microscopy-based Automatic Defect Inspection for Semiconductor Manufacturing: A Systematic Review" was published by researchers at KU Leuven and imec. Abstract: "In this review, automatic defect inspection algorithms that analyze Electron Microscope (EM) images of Semiconductor Manufacturing (SM) products are identified, categorized, and discussed. Thi... » read more

Big Changes In Optical Inspection


Optical inspection always has been the workhorse technology for finding defects in chips. It's fast, cost-efficient, and generally reliable enough for most chips. But as logic scales into the angstrom range, and as systems become collections of chiplets, optical inspection needs to be combined with other types of inspection such as X-ray and acoustic. Kyle Vander Schaaf, application engineer at... » read more

X-ray Inspection Becoming Essential In Advanced Packaging


X-ray technology is moving into the mainstream of chip manufacturing as complex assemblies and advanced packaging make it increasingly difficult to ensure these devices will work as expected throughout their lifecycles. A single defect in a chiplet or interconnect can transform a complex advanced package into expensive scrap, and the risk only increases as the chip industry shifts from homog... » read more

Progress In Wafer And Package Level Defect Inspection


The technology to enable sampling and the need for more metrology and inspection data in a production setting have aligned just in time to address the semiconductor industry’s newest and most complex manufacturing processes. In both wafer and assembly manufacturing, engineering teams have long relied on imaging tools to measure critical features and to inspect for defects after specific pr... » read more

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