Author's Latest Posts

Promising Materials Beyond Silicon (TI, AIXTRON, imec)
By Technical Paper Link - 03 Dec, 2024 - Comments: 0

A new technical paper titled "Future materials for beyond Si integrated circuits: a Perspective" was published by researchers at Texas Instruments, AIXTRON SE and imec. Abstract: "The integration of novel materials has been pivotal in advancing Si-based devices ever since Si became the preferred material for transistors, and later, integrated circuits. New materials have rapidly been adopte... » read more

98 Hardware Security Failure Scenarios (NIST)
By Technical Paper Link - 03 Dec, 2024 - Comments: 0

A new technical paper titled "Hardware Security Failure Scenarios: Potential Hardware Weaknesses" was published by NIST. Abstract "Hardware is often assumed to be robust from a security perspective. However, chips are both created with software and contain complex encodings (e.g., circuit designs and firmware). This leads to bugs, some of which compromise security. This publication evaluate... » read more

Manipulating Diamond Surface Chemistry By UV Laser Etching (Macquarie Univ., MIT)
By Technical Paper Link - 03 Dec, 2024 - Comments: 0

A new technical titled "The effects of sub-monolayer laser etching on the chemical and electrical properties of the (100) diamond surface" was published by researchers at Macquarie University and MIT. Abstract "Tailoring the surface chemistry of diamond is critical to a range of applications from quantum science to electronics. It has been recently shown that dosing the diamond surface with... » read more

Patterning Doping On Very Large Monolayer MoS2 (NREL)
By Technical Paper Link - 03 Dec, 2024 - Comments: 0

A new technical paper titled "Spatially Precise Light-Activated Dedoping in Wafer-Scale MoS2 Films" was published by researchers at National Renewable Energy Laboratory (NREL) and Renewable & Sustainable Energy Institute (RASEI). "In this work, we unravel the mechanism that drives PL* changes of MoS2 monolayers under laser illumination in ambient conditions. We demonstrate the critical ... » read more

The Vulnerability of Clock Trees to Asymmetric Aging
By Technical Paper Link - 03 Dec, 2024 - Comments: 0

A new technical paper titled "The Impact of Asymmetric Transistor Aging on Clock Tree Design Considerations" was published by researchers at Israel Institute of Technology and The Hebrew University of Jerusalem. Abstract "Ensuring integrated circuits (ICs) operate reliably throughout their expected service life is more vital than ever, particularly as they become increasingly central to mis... » read more

Chiplet-Based NPUs to Accelerate Vehicular AI Perception Workloads
By Technical Paper Link - 02 Dec, 2024 - Comments: 0

A new technical paper titled "Performance Implications of Multi-Chiplet Neural Processing Units on Autonomous Driving Perception" was published by researchers at UC Irvine. Abstract "We study the application of emerging chiplet-based Neural Processing Units to accelerate vehicular AI perception workloads in constrained automotive settings. The motivation stems from how chiplets technology i... » read more

STCO for Dense Edge Architectures using 3D Integration and NVM (imec,, et al.)
By Technical Paper Link - 27 Nov, 2024 - Comments: 0

A new technical paper titled "System-Technology Co-Optimization for Dense Edge Architectures using 3D Integration and Non-Volatile Memory" was published by researchers at imec, INESC-ID, Université Libre de Bruxelles, et al. "In this paper, we present an system-technology co-optimization (STCO) framework that interfaces with workload-driven system scaling challenges and physical design-enab... » read more

Gate-All-Around: TCAD and DTCO Approach To Evaluate Power and Performance (imec, et al.)
By Technical Paper Link - 27 Nov, 2024 - Comments: 0

A new technical paper titled "Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: a TCAD-DTCO Study at 90 nm & 120 nm Cell Height" was published by imec, Huawei Technologies and Global TCAD Solutions. Abstract "This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power an... » read more

Critical Design Considerations For High-Bandwidth Chiplet Interconnects (TSMC)
By Technical Paper Link - 26 Nov, 2024 - Comments: 0

A new technical paper titled "High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions" was published by researchers at TSMC. Abstract: "The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by Artificial Intelligence a... » read more

Pooling CPU Memory for LLM Inference With Lower Latency and Higher Throughput (UC Berkeley)
By Technical Paper Link - 26 Nov, 2024 - Comments: 0

A new technical paper titled "Pie: Pooling CPU Memory for LLM Inference" was published by researchers at UC Berkeley. Abstract "The rapid growth of LLMs has revolutionized natural language processing and AI analysis, but their increasing size and memory demands present significant challenges. A common solution is to spill over to CPU memory; however, traditional GPU-CPU memory swapping ofte... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy