Author's Latest Posts

Surface Modification for III-V Selective Area MBE of Non-Selective Mask Materials (UT Austin, Harvard)
By Technical Paper Link - 02 Jun, 2026 - Comments: 0

Researchers from University of Texas at Austin and Harvard University published “Surface Modification for III-V Selective Area Molecular Beam Epitaxy of Non-Selective Mask Materials”. Abstract Excerpt “Selective-area embedded regrowth of III-V semiconductors by molecular beam epitaxy enables the seamless integration of metals and dielectrics into crystalline material for novel... » read more

Scaling Open-Source HW Accelerator for Deep NN Inference (UDE, Fraunhofer IMS)
By Technical Paper Link - 02 Jun, 2026 - Comments: 0

Researchers from University of Duisburg-Essen and Fraunhofer Institute for Microelectronic Circuits and Systems have published “OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs”. Abstract “The increasing computational complexity of deep neural network inference poses significant challenges for efficient hardware acceleration on embedded platforms, particularly with respect ... » read more

Moving Intelligence Closer to the Sensor Edge (IBM Research)
By Technical Paper Link - 02 Jun, 2026 - Comments: 0

A researcher from IBM Research - Europe published “Emerging Trends in Intelligent Sensing”. Abstract “The rapid proliferation of artificial intelligence, connected devices, and high speed mobile networks is driving unprecedented computational demands that challenge traditional sensor architectures. This article explores the shift toward edge computing, where computation is perfor... » read more

Flexible AI-MCU For Fast Inference of Transformer Models At The Ultra-Low-Power Edge (ETH Zurich, U. Bologna)
By Technical Paper Link - 02 Jun, 2026 - Comments: 0

Researchers from ETH Zurich and University of Bologna have released “CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees”. Abstract “We present Chimera, a flexible and scalable Microcontroller Unit (MCU) designed to accelerate real-time inference of rapidly evolving transformer-based models a... » read more

Building Fixed HW Implementations of Neural Networks (Yale, Cornell et al.)
By Technical Paper Link - 29 May, 2026 - Comments: 0

Researchers from Yale University, Cornell University, Boston University, and NTT Research have published “Physical Foundation Models: Fixed hardware implementations of large-scale neural networks”. Abstract "Foundation models are deep neural networks (such as GPT-5, Gemini~3, and Opus~4) trained on large datasets that can perform diverse downstream tasks -- text and code generation, q... » read more

Characterization of GPU-based Inference for Reasoning-Centric LLMs (Micron, Argonne)
By Technical Paper Link - 26 May, 2026 - Comments: 0

Researchers from Micron Technology and Argonne National Laboratory have released “Understanding Inference Scaling for LLMs: Bottlenecks, Trade-offs, and Performance Principles”. Abstract “The transition from standard generative AI to reasoning-centric architectures, exemplified by models capable of extensive Chain-of-Thought (CoT) processing, marks a fundamental paradigm shift i... » read more

Detecting Defect-Induced Silent Data Corruptions in CPUs (Stanford, Google)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Stanford University and Google have published “ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions”. Abstract “Hyperscaler reports of silent data corruptions (SDCs)—presumed to be caused by silicon manufacturing defects—have motivated the development of functional tests for detecting defective CPUs and their use in h... » read more

Impact of Band-to-Band Tunneling in the CTL of V-NAND Flash Memory (U. of Seoul, Samsung)
By Technical Paper Link - 25 May, 2026 - Comments: 0

A new technical paper, "Impact of Band-to-Band Tunneling in the Charge Trap Layer of NAND Flash Memory," was published by researchers from University of Seoul and Samsung Electronics. Abstract "This article investigates the impact of band-to-band tunneling (BTBT) occurring in the charge trap layer (CTL) of vertical NAND (V−NAND) flash memory under excessive erasure conditions and aggres... » read more

An Agent-Driven End-to-End HW-SW Co-Design Benchmark for Heterogeneous SoCs (Columbia, IBM)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Columbia University and IBM Research have released “HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip”. Abstract “Large language models (LLMs) are adopted for software and hardware design, yet these domains are still evaluated separately. Software benchmarks typically assume fixed hardware targets, while hardware be... » read more

Side-Channel Risks Across 2.5D/3D Integration and Chiplet-Based Systems (Grenoble INP – UGA et al.)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Grenoble INP - UGA, CNRS, TIMA have released “Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems”. Abstract “Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, a... » read more

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