Author's Latest Posts


Monitor Etch Defects on Dies in the Outer Regions Of The Wafer Using ISR


A technical paper titled "Detection of defective chips from nanostructures with a high-aspect ratio using hyperspectral imaging and deep learning" was published by researchers at Samsung Electronics. Abstract: "We have developed an imaging spectroscopic reflectometry (ISR) method based on hyperspectral imaging and deep learning to detect defects in the bottom region of high-aspect-ratio nan... » read more

Backpropagation Algorithm On Neuromorphic Spiking HW (U. Of Zurich, ETH Zurich, LANL)


A new technical paper titled "The backpropagation algorithm implemented on spiking neuromorphic hardware" was published by University of Zurich, ETH Zurich, Los Alamos National Laboratory, Royal Institution, London, et al. "This study presents a neuromorphic, spiking backpropagation algorithm based on synfire-gated dynamical information coordination and processing implemented on Intel’s Lo... » read more

Direct-To-Chip Liquid-Cooled Data Centers (Binghamton, Nvidia)


A new technical paper titled "Parameters of performance: A deep dive into liquid-to-air CDU assessment" was published by researchers at Binghamton University-SUNY and NVIDIA. Abstract: "The rapid growth in data center workloads and the increasing complexity of modern applications have led to significant contradictions between computational performance and thermal management. Traditional air... » read more

Schottky Barrier Transistors Roadmap (Univ. of Surrey, NaMLab, PGI et al.)


A new technical paper titled "Roadmap for Schottky Barrier Transistors" was published by researchers at University of Surrey, NaMLab gGmbH, Forschungszentrum Jülic, Peter Grünberg Institute, et al. Abstract: "In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier, as an asset ... » read more

Ge-Based Multigate SBFETs Operated In An NDR Mode (TU Wien, JKU)


A new technical paper titled "Implementation of Negative Differential Resistance-Based Circuits in Multigate Ge Transistors" was published by researchers at TU Wien and JKU (Johannes Kepler University). Abstract: "The co-integration of negative differential resistance (NDR) and Si-based CMOS technology might be a promising concept for multimode devices and circuits with enhanced performance... » read more

Sustainable Hardware Specialization Through Reconfigurable Logic (NUS, Ghent Univ.)


A  new technical paper titled "Sustainable Hardware Specialization" was published by researchers at National University of Singapore and Ghent University. "We explore sustainable hardware specialization through reconfigurable logic that has the potential to drastically reduce the environmental footprint compared to a sea of accelerators by amortizing its embodied footprint across multiple a... » read more

Analysis And Design Of Dual-Layer TFTs (Oregon State Univ., Applied Materials)


A new technical paper titled "Dual-Layer Thin-Film Transistor Analysis and Design" was published by researchers at Oregon State University and Applied Materials. Abstract "A set of analytical equations is formulated for the analysis and design of a dual-layer thin-film transistor (TFT). For a given TFT structure, in which each channel layer thickness is specified, drain current is calculate... » read more

Distributed Shared Memory That Enlarges Effective Memory Capacity Through Intelligent Tiered DRAM and Storage Management (IIT)


A new technical paper titled "MegaMmap: Blurring the Boundary Between Memory and Storage for Data-Intensive Workloads" was published by researchers at Illinois Institute of Technology. "In this work, we propose MegaMmap: a software distributed shared memory (DSM) that enlarges effective memory capacity through intelligent tiered DRAM and storage management. MegaMmap provides workload-aware d... » read more

Dedicated 3D Accelerator Specifically Designed For Emerging Spiking Transformers


A new technical paper titled "Spiking Transformer Hardware Accelerators in 3D Integration" was published by researchers at UC Santa Barbara, Georgia Tech and Burapha University. "Recognizing the current lack of dedicated hardware support for spiking transformers, this paper presents the first work on 3D spiking transformer hardware architecture and design methodology. We present an architect... » read more

Systems-in-Package: Authenticated Partial Encryption Protocol For Secure Testing (U. of Florida)


A new technical paper titled "GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package" was published by researchers at University of Florida and University of Central Florida. Abstract: "A heterogeneous integrated system in package (SIP) system integrates chiplets outsourced from different vendors into the same substrate for better performance. However, during post-integra... » read more

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