Author's Latest Posts


Low-Overhead Fault-Tolerant Quantum Memory (IBM)


A new technical paper titled "High-threshold and low-overhead fault-tolerant quantum memory" was published by researchers at IBM Quantum. Abstract "The accumulation of physical errors prevents the execution of large-scale algorithms in current quantum computers. Quantum error correction promises a solution by encoding k logical qubits onto a larger number n of physical qubits, such t... » read more

Scalable Verification of Memory Consistency (Purdue University)


A new technical paper titled "QED: Scalable Verification of Hardware Memory Consistency" was published by researchers at Purdue University. Abstract "Memory consistency model (MCM) issues in out-of-order-issue microprocessor-based shared-memory systems are notoriously non-intuitive and a source of hardware design bugs. Prior hardware verification work is limited to in-order-issue processors... » read more

Rowhammer Exploitation On AMD Platforms, DDR4 DDR5 (ETH Zurich)


A new technical paper titled "ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms" was published by researchers at ETH Zurich. The work will be presented at USENIX Security Symposium in August 2024. Abstract: "AMD has gained a significant market share in recent years with the introduction of the Zen microarchitecture. While there are many recent Rowhammer attacks launched from Intel CPU... » read more

Power Sub-Mesh Construction To Mitigate IR Drop And Minimize Routing Overhead (Intel)


A new technical paper titled "Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization" was published by researchers at Intel Corporation and National Taiwan University. Abstract: "Multiple power domain design is prevalent for achieving aggressive power savings. In such design, power delivery to cross-domain cells poses a tough challenge at adv... » read more

Hybrid All-Optical Switching Devices Combining Silicon Nanocavities And 2D Semiconductor Material


A new technical paper titled "Hybrid silicon all-optical switching devices integrated with two-dimensional material" was published by researchers at RIKEN, National Institute of Advanced Industrial Science and Technology (AIST), and Keio University. Abstract "We propose and demonstrate hybrid all-optical switching devices that combine silicon nanocavities and two-dimensional semiconduct... » read more

High-Temp, High-Electron Mobility MOSFETs Based On N-Type Diamond


A new technical paper titled "High-Temperature and High-Electron Mobility Metal-Oxide-Semiconductor Field-Effect Transistors Based on N-Type Diamond" was published by researchers at National Institute for Materials Science (Japan). Abstract: "Diamond holds the highest figure-of-merits among all the known semiconductors for next-generation electronic devices far beyond the performance of c... » read more

Electrically Controlled All-AFM Tunnel Junctions on Silicon with Large Room-Temperature Magnetoresistance (Northwestern)


A new technical paper titled "Electrically Controlled All-Antiferromagnetic Tunnel Junctions on Silicon with Large Room-Temperature Magnetoresistance" was published by researchers at Northwestern University, Universitat Jaume, California State University Northridge, Argonne National Lab, Politecnico diBari, and University of Messina. Abstract "Antiferromagnetic (AFM) materials are a pathway... » read more

New Memory Architecture For Local Differential Privacy in Hardware


A technical paper titled "Two Birds with One Stone: Differential Privacy by Low-power SRAM Memory" was published by researchers at North Carolina State University, University of South Alabama, and University of Tennessee. Abstract "The software-based implementation of differential privacy mechanisms has been shown to be neither friendly for lightweight devices nor secure against side-channe... » read more

Optimizing Event-Based Neural Network Processing For A Neuromorphic Architecture


A new technical paper titled "Optimizing event-based neural networks on digital neuromorphic architecture: a comprehensive design space exploration" was published by imec, TU Delft and University of Twente. Abstract "Neuromorphic processors promise low-latency and energy-efficient processing by adopting novel brain-inspired design methodologies. Yet, current neuromorphic solutions still str... » read more

Verifying Hardware CWEs in RTL Designs Generated by GenAI


A new technical paper titled "All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification" was published by researchers at Infineon Technologies. Abstract "Modern hardware designs have grown increasingly efficient and complex. However, they are often susceptible to Common Weakness Enumerations (CWEs). This paper is focused on the formal verification of CWEs in a dataset... » read more

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