Speeding Up Process Optimization Using Virtual Fabrication


Author: Joseph Ervin Director, Semiconductor Process and Integration Lam Research Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patte... » read more

Power/Performance Bits: Dec. 31


Three-valued memory Scientists at the Tokyo Institute of Technology and the University of Tokyo developed a new three-valued memory device inspired by solid lithium-ion batteries which could potentially serve as low power consumption RAM. The new device consisted of a stack of three solid layers made of lithium, lithium phosphate, and gold. This stack is essentially a miniature low-capacity... » read more

A New Dawn For IP


The IP industry is changing again. The concept started as build once, use everywhere, but today it is more like architect once, customize everywhere. Few designs can afford sub-optimal IP for their application. The need for customized IP is driven by both leading-edge designs and the trailing markets, although for different reasons. While this customization is causing IP companies to transfo... » read more

Machine Learning At The Edge


Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet n... » read more

Improving Reliability Monitoring Of High-Bandwidth Memory


As the quest for increased bandwidth and speed continues, multi-die technologies with advanced memory architectures are introduced. As the complexity of these heterogenous packaging continues to develop, new reliability challenges arise. A new approach to HBM subsystem monitoring and repair provides advanced in-field reliability assurance. By applying analytics to data created by on-chip Age... » read more

Why Standard Memory Choices Are So Confusing


System architects increasingly are developing custom memory architectures based upon specific use cases, adding to the complexity of the design process even though the basic memory building blocks have been around for more than half a century. The number of tradeoffs has skyrocketed along with the volume of data. Memory bandwidth is now a gating factor for applications, and traditional memor... » read more

GDDR6 Pushes The Memory Envelope For AI And ADAS


Memory bandwidth is an ever-increasing critical bottleneck for a wide range of use cases and applications. These include artificial intelligence (AI), machine learning (ML), advanced driver-assistance systems (ADAS), as well as 5G wireless and wireline infrastructure. In addition to memory bottlenecks, the above-mentioned use cases and applications are rapidly hitting the real-world limits of t... » read more

Tricky Tradeoffs For LPDDR5


LPDDR5 is slated as the next-gen memory for AI technology, autonomous driving, 5G networks, advanced displays, and leading-edge camera applications, and it is expected to compete with GDDR6 for these applications. But like all next-gen applications, balancing power, performance, and area concerns against new technology options is not straightforward. These are interesting times in the memory... » read more

Power/Performance Bits: Oct. 15


Probabilistic computing Researchers at Purdue University and Tohoku University built a hardware demonstration of a probabilistic computer utilizing p-bits to perform quantum computer-like calculations. The team says probabilistic computing could bridge the gap between classical and quantum computing and more efficiently solve problems in areas such as drug research, encryption and cybersecurit... » read more

Pushing Memory Harder


In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

← Older posts