DDR5 MRDIMM: A Transformational Evolution For DDR5 DIMM


DDR5 is the latest generation of DDR server memory capable of supporting data rates of up to 9,200 Mbps, which is a huge leap over the previous generation of DDR memories. It is used in a wide variety of applications, with the huge server and data center market being the key driver behind the adoption of DDR5-based memory systems. As systems move towards more CPU cores, bandwidth, and capacity,... » read more

Reduce Memory Redesigns With Shift-Left


Engineering managers overseeing memory design know the pattern well: a promising architecture moves smoothly through schematic capture and into layout, only to stumble when integration testing reveals contention issues that force expensive redesigns. Address decoders that looked correct in isolation turn out to enable multiple banks simultaneously. Power switches configured for aggressive gatin... » read more

SOCAMM2: Bringing LPDDR5X Benefits To AI Servers


The rapid scaling of artificial intelligence is reshaping nearly every dimension of data center design. While much of the focus has been on GPUs, accelerators and advanced packaging, another constraint is emerging as equally critical: power. As AI models grow larger and more complex, power consumption, not raw compute, is increasingly the limiting factor in system scalability. Modern AI work... » read more

New CPU Memory Module


Moving data has become the top challenge inside data centers. There is more data to process, more to move, and more to store and retrieve from memory. This is where small outline compression attached memory modules (SOCAMMs) fit in. Frank Ferro, group director for product management at Cadence, talks about the benefits of this next-gen modular low-power memory standard, how it compares with oth... » read more

Chip Industry Week In Review


Deals Marvell acquired Polariton Technologies, a Swiss developer of plasmonics-based silicon photonics devices. Onto Innovation is partnering with Rigaku, combining Onto’s analysis software with Rigaku’s CD-SAXS platform for advanced semiconductor process control. Onto also agreed to acquire a 27% stake in Rigaku for about $710M. Tesla plans to use Intel’s 14A process for its T... » read more

Research Bits: Apr. 21


Compute-in-memory state space models Researchers from the University of Michigan mapped complex state space models directly onto a compute-in-memory architecture in an example of hardware-software co-design for edge AI. "Compute-in-memory systems offer very high energy efficiency and throughput, but they are rigid and not optimal for convolution and transformer networks. In this study, we s... » read more

Early HBM4 Validation Points The Way For Next Generation AI And HPC Systems


As AI and high‑performance computing systems continue to scale, memory bandwidth has emerged as a primary system‑level constraint. Larger models, higher compute density, and increasingly complex multi‑die designs are driving the need for memory interfaces that can deliver extreme bandwidth while operating within tight power and signal‑integrity margins. High‑Bandwidth Memory (HBM) has... » read more

DRAM’s Whac‑A‑Mole Security Crisis


Key takeaways: Rowhammer remains a DRAM security threat, while Rowpress has increasingly become a related threat. New commands issued by the memory controller can help manage refreshes, but they’re not a perfect solution. A smaller, vertical DRAM cell may eliminate the problem, but it’s years away. Rowhammer has been a persistent DRAM issue across several memory generati... » read more

AI Demand Resets Memory Market Priorities, Tightening NOR Flash Availability


The memory sector is entering a major turning point as the industry adjusts to what many now call the AI memory supercycle. Although most headlines focus on high bandwidth memory (HBM) and advanced NAND fueling the rapid expansion of AI data centers, a quieter but important consequence is emerging: shifts in production priorities are beginning to affect the supply of NOR flash across a wide ra... » read more

Reinventing Embedded Memory: Solving The SRAM Scaling Wall


As AI, automotive, and data centers continue to scale exponentially, one part of the chip has quietly become a bottleneck: embedded memory. Modern designs now dedicate more than half of their silicon area to SRAM, yet SRAM no longer scales with Moore's law in advanced CMOS nodes. The result? Larger chips, higher power, and rising costs. RAAAM is a deep-tech startup spun out of Bar-Ilan Unive... » read more

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