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Week In Review: Design, Low Power


Inphi Corporation and Synopsys finalized the acquisition of eSilicon. Synopsys acquired certain IP assets from eSilicon, including TCAMs and multi-port memory compilers, as well as its Interface IP portfolio with High-Bandwidth Interface (HBI) IP and a team of R&D engineers; it did not disclose terms of the deal. Inphi Corporation bought the rest of the company for approximately $216 millio... » read more

CEO Outlook: 2020 Vision


The start of 2020 is looking very different than the start of 2019. Markets that looked hazy at the start of 2019, such as 5G, are suddenly very much in focus. The glut of memory chips that dragged down the overall chip industry in 2019 has subsided. And a finely tuned supply chain that took decades to develop is splintering. A survey of CEOs from across the industry points to several common... » read more

What Worked, What Didn’t In 2019


2019 has been a tough year for semiconductor companies from a revenue standpoint, especially for memory companies. On the other hand, the EDA industry has seen another robust growth year. A significant portion of this disparity can be attributed to the number of emerging technology areas for semiconductors, none of which has reached volume production yet. Some markets continue to struggle, a... » read more

Week In Review: Design, Low Power


M&A eSilicon will be acquired by Inphi Corporation and Synopsys. Inphi is acquiring the majority of the company, including the ASIC business and 56/112G SerDes design and related IP, for $216 million in both cash and the assumption of debt. Inphi expects to combine its DSP, TiA, Driver and SiPho products with eSilicon’s 2.5D packaging and custom silicon design capabilities for electro-optics... » read more

Speeding Up 3D Design


2.5D and 3D designs have garnered a lot of attention recently, but when should these solutions be considered and what are the dangers associated with them? Each new packaging option trades off one set of constraints and problems for a different set, and in some cases the gains may not be worth it. For other applications, they have no choice. The tooling in place today makes it possible to de... » read more

ML, Edge Drive IP To Outperform Broader Chip Market


The market for third-party semiconductor IP is surging, spurred by the need for more specific capabilities across a wide variety of markets. While the IP industry is not immune to steep market declines in semiconductor industry, it does have more built-in resilience than other parts of the industry. Case in point: The top 15 semiconductor suppliers were hit with an 18% decline in 2019 first-... » read more

Week In Review: Design, Low Power


eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more

Long And Longer Reach SerDes – On The Road Again


We’ve had the pleasure of participating in two events over the past two weeks. I wouldn’t recommend doing two major shows back-to-back, but it has been exhilarating and quite interesting. Our “road trip” began last week in Mountain View for the second annual AI Hardware Summit. You’ve probably noticed you can go to an AI-related show every week (or more) if you like. The trick is to f... » read more

Opposites Attract: IP Standardization vs. Customization


Have you had a look lately at an autonomous driving SoC? Have you noticed, besides the cool machine learning stuff, the grocery list of third-party IP that goes into it? It is a long, long list, composed of pieces both big and small and quite diverse. For example, interface and peripheral PHYs and controllers, memories, on-chip interconnects, PVT monitors and PLLs. In some highly-publicized exa... » read more

3D Power Delivery


Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more

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