3D Power Delivery


Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more

Chiplets, Faster Interconnects, More Efficiency


Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency. Taken as a whole, this represents a significant shift in direction for the major chip companies. All of them are wrestling with massive increases in processing demands ... » read more

Chiplets: Open Market or Joint Venture?


By Dr. Carlos Macián, senior director AI Strategy & Products, eSilicon Corporation “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” — Gordon Moore, 1965 “Chiplet” has become a buzzword and like most of its kind, the success of the buzzword predates the widespread availability of the produ... » read more

Optimizing Power For Learning At The Edge


Learning on the edge is seen as one of the Holy Grails of machine learning, but today even the cloud is struggling to get computation done using reasonable amounts of power. Power is the great enabler—or limiter—of the technology, and the industry is beginning to respond. "Power is like an inverse pyramid problem," says Johannes Stahl, senior director of product marketing at Synopsys. "T... » read more

HBM2E: The E Stands for Evolutionary


Samsung introduced the first memory products in March that conform to JEDEC’s HBM2E specification, but so far nothing has come to market—a reflection of just how difficult it is to manufacture this memory in volume. Samsung’s new HBM2E (sold under the Flashbolt brand name, versus the older Aquabolt and Flarebolt brands), offers 33% better performance over HBM2 thanks to doubling the de... » read more

Are Digital Twins Something For EDA To Pursue?


‘Digital Twins’ are one of the new, fashionable key concepts for system developers, but do they fit with EDA? How many different types of engines do these twins run on – abstract simulation, signal-based RTL simulation, emulation, prototyping, actual silicon? What should the use models be called for digital twinning – like reproduction of bugs from silicon in emulation? Or optimizing th... » read more

More Semiconductor Data Moving To Cloud


The cloud is booming. After years of steady growth it has begun to spike, creating new options for design, test, analytics and AI, all of which have an impact on every segment of the semiconductor industry. The initial idea behind the cloud is that it would supplement processing done on premises, adding extra processing power wherever necessary, such as in the verification and debug stages o... » read more

Power Is Limiting Machine Learning Deployments


The total amount of power consumed for machine learning tasks is staggering. Until a few years ago we did not have computers powerful enough to run many of the algorithms, but the repurposing of the GPU gave the industry the horsepower that it needed. The problem is that the GPU is not well suited to the task, and most of the power consumed is waste. While machine learning has provided many ... » read more

Memory IP: From Cobblestone To Cornerstone


Embedded, on-chip SRAM has been a fundamental building block for custom and standard chips for quite a while. When all this began, there were typically small SRAM blocks of on-chip memory supplemented by off-chip DRAM devices. Those off-chip devices became more sophisticated, with higher performance interfaces (e.g., GDDR6) or new form factors (e.g., HBM2 3D memory stacks). The on-chip memory p... » read more

Node Within A Node


Enough margin exists in manufacturing processes to carve out the equivalent of a full node of scaling, but shrinking that margin will require a collective push across the entire semiconductor manufacturing supply chain. Margin is built into manufacturing at various stages to ensure that chips are manufacturable and yield sufficiently. It can include everything from variation in how lines are... » read more

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