Week In Review: Design, Low Power

Inphi, Synopsys buy eSilicon; Synopsys acquires DINI Group; die-to-die PHY; PCIe 5.0 IP.


eSilicon will be acquired by Inphi Corporation and Synopsys. Inphi is acquiring the majority of the company, including the ASIC business and 56/112G SerDes design and related IP, for $216 million in both cash and the assumption of debt. Inphi expects to combine its DSP, TiA, Driver and SiPho products with eSilicon’s 2.5D packaging and custom silicon design capabilities for electro-optics, 5nm advanced CMOS process node, and custom DSP solutions. Inphi says the acquisition will expand its reach in cloud data center networking and telecom 5G infrastructure in addition to adding new engineering design centers.

Concurrently, Synopsys will acquire eSilicon’s embedded memory portfolio of SRAM, TCAM, multi-port memory compiler IP and high-bandwidth memory (HBM) and high-bandwidth interface (HBI) IP assets. A team of R&D engineers will also join Synopsys. Terms of the Synopsys purchase were not disclosed. eSilicon was founded in 2000.

Synopsys acquired The DINI Group. The DINI Group specializes in large FPGA boards for SoC/ASIC prototyping and emulation as well as high-performance computing and high-frequency/low latency algorithmic trading. Based in La Jolla, CA, DINI Group was founded in 1995. Terms of the deal were not disclosed.

Tools & IP
Cadence unveiled its UltraLink D2D PHY IP, a high-performance, low-latency PHY for die-to-die connectivity in chiplet and system-in-package applications targeted at the AI/ML, 5G, cloud computing and networking market segments. It supports multi-chip modules on organic substrates and provides up to 40Gbps wire speed in an NRZ serial interface, and up to 1Tbps/mm unidirectional bandwidth. The IP includes built-in de-skew and scrambling/de-scrambling logic and requires 28 data wires for 1Tbps bandwidth. The D2D PHY IP also offers latency as low as 5ns round trip from receiver to transmitter, utilizes standard non-return-to zero (NRZ) coding and achieves better than 10-15 bit error rate (BER) without requiring forward error correction (FEC).

Rambus debuted a PCIe 5.0 interface solution including both PHY and digital controller from the recently-acquired Northwest Logic. It provides 32 GT/s bandwidth per lane with 128 GB/s bandwidth in x16 configuration as well as multi-tap transceiver and receiver equalization to compensate for more than 36dB of insertion loss. In addition to PCIe, the PHY supports Compute Express Link (CXL) connectivity between host processor and workload accelerators for heterogenous computing. It is available in a 7nm FinFET process and backward compatible to PCIe 4.0, 3.0, and 2.0.

Mentor expanded its Tessent tools with Connect and Safety. Tessent Connect is a DFT automation methodology for intent-driven hierarchical test implementation. It includes automation of setup, connectivity and pattern generation tasks for shorter turn-around times. The Tessent Safety open ecosystem provides a portfolio of automotive IC test solutions from Mentor with links to its industry partners such as the Arm Functional Safety Partnership Program.

Xilinx made its new Vitis unified software platform and optimized open source libraries available to download without charge. Vitis aims to provide a way for software developers to utilize Xilinx hardware to accelerate applications without specific hardware development expertise.

Aldec expanded its FPGA Mezzanine Card (FMC) product line to support various applications in the areas of IIoT, Networking, Embedded Vision and Automotive. The PMC connectors are based on High Pin Count type compliant with ANSI/VITA 57.1. They provide individual signaling speed of up to 25 Gb/s per link and overall bandwidth of 200 Gb/s between the daughter card and carrier card for selected configurations.

Xilinx also added two devices to its 16nm automotive line. The Zynq UltraScale+ MPSoC 7EV and 11EG offer over 650,000 programmable logic cells and nearly 3,000 DSP slices. The XA 7EV contains a video codec unit for h.264/h.265 encode and decode, while the XA 11EG includes 32 12.5Gb/s transceivers and provides four PCIe Gen3x16 blocks.

Efinix uncorked its Trion T120 FPGAs, featuring a small, high-density fabric, a hardened DDR memory controller and hardened MIPI CSI-2 and PHY interfaces. They are targeted for edge AI applications.

GOWIN Semiconductor added integrated Bluetooth 5.0 Low Energy radio to its latest mSoC FPGA. The GW1NRF-4 provides a 4k LUT FPGA, a 32-bit power-optimized ARC processor and the BLE radio in a single 6x6mm QFN package. It includes a power management unit, which allows for various power modes along with a full chip disable feature to turn off the device while consuming 5nA.

Samsung Foundry used Synopsys’ TestMAX XLBIST solution on an automotive IC to provide dynamic in-system testing for critical failures in order to meet automotive functional safety requirements. The tool has been included as part of Samsung’s automotive reference flow for RTL-to-GDSII design.

Tunisian energy metering company SIAME included Adesto Technologies’ non-volatile memory (NVM) and Power Line Communications chips in a new G3-PLC smart meter that is beginning pilot production.

Himax incorporated Synopsys’ DesignWare ARC Data Fusion IP Subsystem into its WiseEye WE-I Plus ASIC platform for deploying CNN-based machine learning models on AI and IoT applications. The subsystem is based on the ARC EM9D with enhanced DSP features and power-efficient hardware acceleration for CDM, HOG, and JPEG algorithms.

Check out upcoming industry events and conferences: Accellera will hold a Proposed Working Group meeting on a potential standard for FMEDA tool interoperability on Dec. 6 at NXP in Munich, Germany. The RISC-V Summit will include talks, an expo, and tutorials on the open ISA Dec. 10-12 in San Jose, CA.

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