Week In Review: Manufacturing, Test


Chipmakers United Microelectronics Corp. (UMC) has announced the readiness of its new 22nm process. The process enables new 22nm designs or allows customers to migrate from 28nm to 22nm. UMC’s 22nm maintains its existing 28nm design architectures. UMC's 22nm process features a 10% area reduction, better power-to-performance ratio and enhanced RF capabilities, compared to the company’s 2... » read more

Designing In 4D


The chip design world is no longer flat or static, and increasingly it's no longer standardized. Until 16/14nm, most design engineers viewed the world in two dimensions. Circuits were laid out along x and y axes, and everything was packed in between those two borders. The biggest problems were that nothing printed as neatly as the blueprint suggested, and current leaked out of two-dimension... » read more

Week In Review: Design, Low Power


M&A eSilicon will be acquired by Inphi Corporation and Synopsys. Inphi is acquiring the majority of the company, including the ASIC business and 56/112G SerDes design and related IP, for $216 million in both cash and the assumption of debt. Inphi expects to combine its DSP, TiA, Driver and SiPho products with eSilicon’s 2.5D packaging and custom silicon design capabilities for electro-optics... » read more

Week in Review: IoT, Security, Automotive


Connectivity, 5G Rambus has revealed a PCI Express 5.0 interface on advanced 7nm finFET process node for heterogenous computing aimed at performance-intensive uses, such as AI, data center, HPC, storage and 400GbE networking. With a PHY and a digital controller core recently acquired Northwest Logic, the interface has 32 GT/s (gigatransfers per second) bandwidth per lane with 128 GB/s bandwidt... » read more

Addressing Pain Points In Chip Design


Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx, Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Less Margin, More Respins, And New Markets


Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx; Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Week In Review: Manufacturing, Test


Packaging and test In a major deal that has some implications in the OSAT supply chain, South Korea’s Nepes has taken over Deca Technologies’ wafer-level packaging manufacturing line in the Philippines. In addition, Nepes has also licensed Deca’s M-Series wafer-level packaging technology. This includes fan-in technology as well as wafer- and panel-level fan-out. It also includes an ad... » read more

Week In Review: Design, Low Power


Synopsys completed its acquisition of QTronic GmbH, a provider of simulation, test tools, and services for automotive software and systems development. Terms of the deal were not disclosed. Synopsys launched the PrimeECO design closure solution, a signoff-driven solution that the company says achieves signoff closure with zero iterations. The tool includes a machine-learning-driven Hybrid Ti... » read more

FPGA Design Tradeoffs Getting Tougher


FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the cost and time of developing an ASIC. But today, both FPGAs and eFPGAs are being used in the most demanding applications, including cloud computing, AI, machine learning, and deep learning. In some ... » read more

Week In Review: Design, Low Power


Xilinx debuted the Virtex UltraScale+ VU19P, which the company says is now the world's largest FPGA at 1.6X the size of its predecessor. The VU19P features 35 billion transistors, 9 million system logic cells, up to 1.5 terabits per-second of DDR4 memory bandwidth and up to 4.5 terabits per-second of transceiver bandwidth, and over 2,000 user I/Os. With a set of debug, visibility tools, and IP,... » read more

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