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Week In Review: Design, Low Power


Cadence's digital full flow was certified for the GlobalFoundries 12LP/12LP+ process platforms. The certified tools include the Innovus Implementation System, Genus Synthesis Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Quantus Extraction Solution, Litho Physical Analyzer (LPA), and Pegasus Verification System. Siemens Digital Industries Software's Calibre nm... » read more

Week In Review: Design, Low Power


Tools & IP MIPS announced its first products based on the RISC-V ISA. The eVocore IP cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a Coherence Manager that maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices. They target high-performan... » read more

Zero Dark Silicon


Planning for AI requires an understanding of how much data needs to be processed and how quickly that needs to happen. Nick Ni, senior director of data center AI and compute markets at AMD, talks with Semiconductor Engineering about data bubbles and domain-specific designs, why dark silicon is no longer as useful as in the past, and how to optimize power and performance in both the data center ... » read more

Week In Review: Design, Low Power


Rambus will acquire Hardent, a provider of design services and IP. Rambus said Hardent's silicon design, verification, compression, and Error Correction Code (ECC) expertise will provide key resources for the Rambus CXL Memory Interconnect Initiative. “Driven by the demands of advanced workloads like AI/ML and the move to disaggregated data center architectures, industry momentum for CXL-base... » read more

Diagnostic Medical Ultrasound Innovation Using UltraFast Algorithms


Medical ultrasound is the most attractive among all diagnostic imaging systems due to its least-invasive nature and lack of any radiation. As medical ultrasound continues to grow in wider range of applications for its non-invasive nature and for its ability to see soft-tissue images, there is growing demand in supporting advanced imaging techniques in ultrasound beamformers, in multi-dimensiona... » read more

System-Level Benefits Of The Versal Platform


Moore's Law has fueled the technological prosperity of the last 50 years, but it is generally believed now that Gordon Moore's 1965 forecast about the pace of innovation no longer holds true today. Continuing the silicon architectures of yesterday cannot meet the expanding demands of tomorrow's workloads. Frequently highlighted by today’s leaders in the field of computer architecture [Ref 1],... » read more

Choosing Which Tasks To Optimize In Chips


The optimization of one or more tasks is an important aspect of every SoC created, but with so many options now on the table it is often unclear which is best. Just a few years ago, most people were happy to buy processors from the likes of Intel, AMD and Nvidia, and IP cores from Arm. Some even wanted the extensibility that came from IP cores like Tensilica and ARC. Then, in 2018, John Henn... » read more

Week In Review: Design, Low Power


Tools & IP Synopsys unveiled a new neural processing unit (NPU) IP and toolchain. DesignWare ARC NPX6 NPU IP scales from 4K to 96K MACs with power efficiency of 30 TOPS/Watt. A single instance offers 250 TOPS at 1.3 GHz on 5nm processes in worst-case conditions, or up to 440 TOPS by using new sparsity features, which can increase the performance and decrease energy demands of executing a n... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Synopsys uncorked its new neural processor IP, which can be used to develop scalable neural processors in automotive and consumer products. The ARC NPX6 NPU IP can run at 3,500 TOPS (30 TOPS per watt), running up to 96K MACs with enhanced utilization, new sparsity features and new interconnect for scalability. The ARC NPX6FS NPU IP and MetaWare MX Toolkit for Safety can be... » read more

More Options, Less Dark Silicon


Chipmakers are beginning to re-examine how much dark silicon should be used in a heterogenous system, where it works best, and what alternatives are available — a direct result of a slowdown in Moore's Law scaling and the increasing disaggregation of SoCs. The concept of dark silicon has been around for a couple decades, but it really began taking off with the introduction of the Internet ... » read more

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