Emulation System for Racetrack Memories Based on FPGA


A technical paper titled “ERMES: Efficient Racetrack Memory Emulation System based on FPGA” was written by researchers at University of Calabria and TU Dresden.

“This paper presents a new emulation system for RTMs based on heterogeneous FPGA-CPU Systems-on-Chips (SoCs). Thanks to its high flexibility, the proposed emulator can be easily configured to evaluate different memory architectures. In addition, the CPU can be used to stimulate the RTM architecture under test with appropriate benchmarks, thus providing a fast self-contained evaluation environment,” states the paper.

Find the technical paper here. 2022.

Fanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar, “ERMES: Efficient Racetrack Memory Emulation System based on FPGA”In Proceeding: 2022 International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-6, Aug 2022.

3D Racetrack Memory Device (Max Planck)

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