tag: emulation

How Far Left Can We Really Shift Verification?
By Frank Schirrmeister - 25 Jun, 2026 - Comments: 0

"Shift left" has been in the engineering lexicon for so long that it risks becoming wallpaper. We nod at it, we put it on slides, and we move on. But the goalposts keep moving. Things that used to live comfortably at the tail end of the design flow — software bring-up, power and performance characterization, thermal analysis — are being dragged earlier and earlier into the schedule, driven ... » read more

Emulation-based SoC Security Verification (U. of Florida)
By Technical Paper Link - 17 Apr, 2026 - Comments: 0

A new technical paper, "Emulation-based System-on-Chip Security Verification: Challenges and Opportunities," was published by researchers at University of Florida. Abstract "Increasing system-on-chip (SoC) heterogeneity, deep hardware/software integration, and the proliferation of third-party intellectual property (IP) have brought security validation to the forefront of semiconductor desig... » read more

SSD Emulator For Massively Parallel, GPU-Centric Storage (KAIST)
By Technical Paper Link - 11 Apr, 2026 - Comments: 0

A new technical paper, "SwarmIO: Towards 100 Million IOPS SSD Emulation for Next-generation GPU-centric Storage Systems," was published by KAIST. Abstract "GPU-initiated I/O has emerged as a key mechanism for achieving high-throughput storage access by leveraging massive GPU thread-level parallelism, while recent industry trends point toward SSDs optimized for ultra-high random-read IOPS.... » read more

Replay‑based Validation as a Scalable Methodology for Chiplet‑based Systems (Intel, Synopsys)
By Technical Paper Link - 18 Mar, 2026 - Comments: 0

A new technical paper, "ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation," was published by researchers at Intel, Nvidia and Synopsys. Abstract "Integration of CPU and GPU technologies is a key enabler for modern AI and graphics workloads, combining control-oriented processing with massive parallel compute capability. As systems evolve toward chiplet-based archite... » read more

Heterogeneous Multicore System IP
By Nayan Gaywala - 29 Jan, 2026 - Comments: 0

For many of today’s embedded applications, compute requirements demand multiple cores (compute units). These applications also run various types of workloads. A heterogeneous multicore system enables designers to reduce energy and area costs while meeting performance requirements across various workloads. Data crunching by these multiple cores also puts a huge demand on the interconnect and m... » read more

Software-Defined Hardware-Assisted Verification: Scaling To Quadrillions Of Cycles For Verification In The AI Era
By Frank Schirrmeister - 23 Dec, 2025 - Comments: 0

The semiconductor industry is at an inflection point. The convergence of advanced multi-die architectures, AI-driven workloads, and rapidly evolving interface protocols is creating unprecedented design complexity. At the same time, market pressures demand faster time-to-market and higher performance, leaving little room for error. From data center to edge developments, users have to run softwar... » read more

Benchmark Before You Build
By Synopsys - 27 Aug, 2025 - Comments: 0

Traditional verification methods, static analysis, RTL simulation and emulation have long depended on constrained-random or targeted test suites to confirm that a design operates as intended. However, none of these approaches accurately reproduce how real users will interact with the silicon once it’s deployed in phones, datacenters, or embedded systems. To stay competitive, the semiconductor... » read more

Locking When Emulating Xtensa LX Multi-Core On A Xilinx FPGA
By Nayan Gaywala - 31 Oct, 2024 - Comments: 0

Today's high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with additional programming complexity, especially when accessing shared memory data structures and hardware peripherals. CPU cores need to access shared data in an atomic fashion in a multi-core environme... » read more

Accelerating The Pace And Precision Of AI Chip Innovation
By Stelios Diamantidis - 29 Aug, 2024 - Comments: 0

The Hot Chips 2024 conference, which took place this week in Silicon Valley, was a showcase for AI chip innovation. The three-day program illustrated the race among both established chipmakers and new entrants to explore advanced architectures and embrace novel design solutions to deliver the next breakthrough AI processor. In this article, I share a few “hot takes” from the conference that... » read more

Communication Is Key To Finding And Fixing Bugs In ICs
By Ann Mutschler and Adam Kovac - 08 May, 2024 - Comments: 0

Experts at the Table: Finding and eliminating bugs at the source can be painstaking work, but it also can prevent even greater problems from developing later on. To examine the best ways to tackle this problem, Semiconductor Engineering sat down with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software product manager ... » read more

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