2 Big Shifts, Lots Of Questions


The proliferation of AI everywhere, and ongoing efforts by big systems companies to develop their own chips, could have a profound effect on semiconductor manufacturing for years to come. AI is a multi-faceted topic, but what makes this particularly interesting from a semiconductor standpoint is the architecture of AI-specific chips. So far, most of these chips have been developed for data c... » read more

A VC View Of The AI Landscape


In this blog post, I’ll highlight my takeaways from the recent AI Hardware Summit where I participated as a panelist. The conference’s focus on developing hardware accelerators for neural networks and computer vision attracted companies from across the ecosystem – AI chip startups, semiconductor companies, system vendors/OEMs, data center providers, financial services companies and VCs,... » read more

EDA Cloud Adoption Hits Speed Bumps


If moving semiconductor design to the Cloud was easy and beneficial, everyone would be doing it. But so far, few have done more than dip a toe. The level of difficulty associated with migrating to the Cloud varies, depending upon who you talk to. The reality is that not everyone makes it as easy as it could be, or is not willing to put the necessary effort into making it easier. There is cer... » read more

What Will Intel Do Next?


The writing is on the wall for big processor makers. Apple, Amazon, Facebook and Google are developing their own processors. In addition, there are more than 30 startups developing various types of AI accelerators, as well as a field of embedded FPGA vendors, a couple of discrete FPGA makers, and a slew of soft processor cores. This certainly hasn't been lost on Intel. As the world's largest... » read more

The Perfect Risk


The development of semiconductors is an act of risk management. Very simply put, if you take on too much risk, it could lead to product failure or a missed market window, both of which can cost $M. For a company that only produces one or two products a year, that can spell total disaster. If you do not take on enough risk, you are probably not going to end up with a competitive product that ... » read more

Betting Big On Discontinuity


Wally Rhines, president and CEO of Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about the booming chip industry, what's driving it, how long it will last and what changes are ahead in EDA and chip architectures. What follows are excerpts of that conversation. SE: The EDA and semiconductor industries are doing well right now. What's driving that growth? Rhine... » read more

Market Trends For Large Volume Semi Products


Material and capacity shortages typically prompt changes in normal operating procedures, especially purchasing strategies. If the uncertainty regarding world trade policies and tariffs are added on top of the shortages, the impact results in unusual gyrations in industry sales data and possible misleading signals. Discretes, analog and opto are the three largest semiconductor product categories... » read more

The Big Blur


Chip companies, research houses, foundries—and more recently large systems companies—have been developing alternative technologies to continue scaling power and performance. It's still not obvious which of those will win, let alone survive, or what they will do to the economics of developing chips. For more than five decades, the biggest concern was scaling devices in order to save money... » read more

Electromagnetic Analysis and Signoff: Cost Savings


By Nikolas Provatas and Magdy Abadir We are often asked by SoC design teams about the benefits of an electromagnetic analysis and signoff methodology. Here is an overview of some of the big “cost savings”. Time to Market Savings Utilizing an EM crosstalk analysis and signoff methodology provides designers with an “insurance policy” against the risk of EM coupling in their SOC des... » read more

System-Level Test: Where Does It Fit?


Our second C-Brief discusses where system-level test (SLT) best fits into your semiconductor test workflow. With automated testing equipment (ATE), a traditional workflow may consist of: Wafer sort (WS) Burn-in after packaging (BI) Combination of structural testing (ST) and functional testing (FT). As demands on high-volume manufacturing shift in response to wider industry and com... » read more

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