tag: advanced packaging

Thermal Challenges In Advanced Packaging
By Ed Sperling - 02 Dec, 2019 - Comments: 1

CT Kao, product management director at Cadence, talks with Semiconductor Engineering about why packaging is so complicated, why power and heat vary with different use cases and over time, and why a realistic power map is essential particularly for AI chips, where some circuits are always on.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTube channel here » read more

Designing In 4D
By Ed Sperling - 26 Nov, 2019 - Comments: 0

The chip design world is no longer flat or static, and increasingly it's no longer standardized. Until 16/14nm, most design engineers viewed the world in two dimensions. Circuits were laid out along x and y axes, and everything was packed in between those two borders. The biggest problems were that nothing printed as neatly as the blueprint suggested, and current leaked out of two-dimension... » read more

Better, Not Best
By Brian Bailey - 26 Nov, 2019 - Comments: 0

The semiconductor industry has been lulled into a particular way of thinking by Moore's Law. It is like the age-old joke — you don't have to outrun a bear, you only have to be faster than your companion. The same has held true for designs. There is little to no point being the best, you only have to be good enough to be better than the competition. That sets the bar. Best is also relative.... » read more

Electromagnetic Challenges In High-Speed Designs
By Ed Sperling - 25 Nov, 2019 - Comments: 0

ANSYS’ Anand Raman, senior director, and Nermin Selimovic, product sales specialist, talk with Semiconductor Engineering about how to deal with rising complexity and tighter tolerances in AI, 5G, high-speed SerDes and other chips developed at the latest process nodes where the emphasis is on high performance and low power. » read more

Is There A Crossover Point For Mainstream Anymore?
By Ed Sperling - 21 Nov, 2019 - Comments: 0

Until 28nm, it was generally assumed that process nodes would go mainstream one or two generations after they were introduced. So by the time the leading edge chips for smartphones and servers were being developed at 16/14nm and 10/7nm, it was assumed that developing a chip at 28nm would be less expensive, less complex, and that the process rule deck would shrink. That worked for decades. Th... » read more

New Trends In Wafer Bonding
By Katherine Derbyshire - 21 Nov, 2019 - Comments: 0

Unable to scale horizontally, due to a combination of lithography delays and power constraints, manufacturers are stacking devices vertically. This has become essential as the proliferation of mobile devices drives demand for smaller circuit footprints, but the transition isn't always straightforward. Three-dimensional integration schemes take many forms, depending on the required interconne... » read more

Speeding Up 3D Design
By Brian Bailey - 14 Nov, 2019 - Comments: 0

2.5D and 3D designs have garnered a lot of attention recently, but when should these solutions be considered and what are the dangers associated with them? Each new packaging option trades off one set of constraints and problems for a different set, and in some cases the gains may not be worth it. For other applications, they have no choice. The tooling in place today makes it possible to de... » read more

Addressing Pain Points In Chip Design
By Ed Sperling - 13 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx, Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Which Verification Engine When
By Ed Sperling - 31 Oct, 2019 - Comments: 0

Frank Schirrmeister, group director for product marketing at Cadence, talks about which tools get used throughout the design flow, from architecture to simulation, formal verification, emulation, prototyping all the way to production, how the cloud has impacted the direction of the flow, and how machine learning will impact verification. » read more

Migrating 3D Into The Mainstream
By Brian Bailey - 31 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for ANSYS' Semiconductor Business Unit; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Business;... » read more

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