Securing Terabit Ethernet For AI: Where MACsec, IPsec, And UET TSS Each Fit (And Why You Need More Than One)


As AI and HPC systems scale, the network has become both a critical enabler of performance and a rapidly expanding attack surface. The shift from rack-scale compute to cluster- and data center-scale AI infrastructure means that data is no longer confined to a single chip, board, or even system. Instead, it moves continuously across hundreds, or thousands, of endpoints, often at aggregate bandwi... » read more

Breaking The “Unhackable” Xbox One


For more than a decade, the Xbox One stood out as one of the most resilient consumer devices ever built. While other consoles from the same era were eventually jailbroken or modified, the Xbox One remained largely untouched. Its layered defenses, hardened boot process, and strong cryptographic foundations earned it a reputation as effectively “unhackable.” That assumption changed at RE//... » read more

Securing Chiplet-Based Platforms: Distributed Trust With Centralized Authority


In previous blogs, From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm, and Developing a Security Framework for Chiplet-based Systems, we discussed why chiplets change the game from a security perspective, and why security must be addressed at a platform-level in a chiplet-based system. In a monolithic device, trust is often implicitly bounded by the die itself: sensitive asse... » read more

How OCP S.O.L.I.D. Completes The Data Center Security Picture


In 2023, the Open Compute Project launched S.A.F.E. (Security Appraisal Framework and Enablement), a standardized process for auditing data center hardware and firmware. It delivered something the industry needed: approved third-party reviewers, continuous assessments, and public reports — not just one-time certifications. S.A.F.E. provided the audit framework; what it did not provide was gui... » read more

DRAM’s Whac‑A‑Mole Security Crisis


Key takeaways: Rowhammer remains a DRAM security threat, while Rowpress has increasingly become a related threat. New commands issued by the memory controller can help manage refreshes, but they’re not a perfect solution. A smaller, vertical DRAM cell may eliminate the problem, but it’s years away. Rowhammer has been a persistent DRAM issue across several memory generati... » read more

Developing A Security Framework For Chiplet-Based Systems


In a previous blog, From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm, we discussed why chiplets change the game from a security perspective, and why security must be addressed at a platform-level in a chiplet-based system. In a monolithic SoC, device identity is often anchored in a single root of trust that owns key material and policy. In a chiplet platform, every security... » read more

Agent Card Poisoning: A Metadata Injection Vulnerability In The Systems Using Google A2A Protocol


Modern multi-agent systems built on the Google A2A protocol enable dynamic discovery and delegation between autonomous agents through structured metadata known as agent cards. These cards describe capabilities, endpoints, and operational details that the host agent uses to plan task delegation. However, when agent cards are injected directly into an LLM’s reasoning context without strict boun... » read more

Importance Of Hardware Security Verification In Pre-Silicon Design


Today’s semiconductor chips run cloud infrastructure, automotive controllers, industrial robots, and edge AI processors, so effectively the entire technology market. Engineers must now ensure that silicon itself defends against attacks, protects embedded secrets, and complies with increasingly stringent global security standards, such as ISO/SAE 21434 and the EU Cyber Resilience Act. Regulato... » read more

Building an AI Chip: Security, Software Development, and Lifecycle Management


The third white paper in our series, "Building an AI Chip" delves into the critical aspects of ensuring robust security and efficient software development for AI chips. As AI applications become increasingly integrated into everyday systems, the need for secure and reliable chip designs is paramount. This paper outlines essential strategies for safeguarding AI chip development, optimizing softw... » read more

Ultra Ethernet Security (UET‑TSS) Tailored For AI And HPC


As AI and high‑performance computing (HPC) systems scale from racks to entire data centers, the network has become both a performance enabler and a growing attack surface. Modern AI fabrics interconnect thousands of GPUs and CPUs, move massive volumes of sensitive model data, and increasingly rely on direct memory access rather than host‑mediated communication. These trends exposed a fundam... » read more

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