Importance Of Hardware Security Verification In Pre-Silicon Design


Today’s semiconductor chips run cloud infrastructure, automotive controllers, industrial robots, and edge AI processors, so effectively the entire technology market. Engineers must now ensure that silicon itself defends against attacks, protects embedded secrets, and complies with increasingly stringent global security standards, such as ISO/SAE 21434 and the EU Cyber Resilience Act. Regulato... » read more

Building an AI Chip: Security, Software Development, and Lifecycle Management


The third white paper in our series, "Building an AI Chip" delves into the critical aspects of ensuring robust security and efficient software development for AI chips. As AI applications become increasingly integrated into everyday systems, the need for secure and reliable chip designs is paramount. This paper outlines essential strategies for safeguarding AI chip development, optimizing softw... » read more

Ultra Ethernet Security (UET‑TSS) Tailored For AI And HPC


As AI and high‑performance computing (HPC) systems scale from racks to entire data centers, the network has become both a performance enabler and a growing attack surface. Modern AI fabrics interconnect thousands of GPUs and CPUs, move massive volumes of sensitive model data, and increasingly rely on direct memory access rather than host‑mediated communication. These trends exposed a fundam... » read more

Limiting AI/ML Tools To Ensure Physical AI Safety, Security


Key Takeaways: AI-based tools can help monitor physical AI systems and LLMs, but human oversight is still needed to avoid false positives, bias, and other anomalies. For autonomous vehicles and robots, edge case scenarios and understanding human values are weak points, especially as moral and social values change over time. AI tools are growing and becoming increasingly helpful for c... » read more

Learnings From The Polish Energy Sector Attacks


On 29 December 2025, coordinated cyberattacks targeted Polish energy infrastructure. The attacks coincided with severe winter weather and appear to have aimed at disrupting heat supply to end users by targeting renewable energy farms. The attackers succeeded in disabling controllers linking generation and distribution facilities but, thankfully, were unable to halt electricity production. Th... » read more

Verifying Scale-Up And Scale-Out In Data Centers


Semiconductor Engineering sat down to discuss challenges and solutions for data center build-out and build-up with Gordon Allan, Siemens EDA director of verification IP; Rishi Chugh, vice president of product marketing for network switching at Marvell; Saravanan Kalinagasamy, senior director of ASIC design and validation at Astera Labs; and Jalaj Gupta, product engineering lead at Siemens EDA. ... » read more

From Monolithic SoCs To Chiplets: A New Hardware Security Paradigm


Chiplet architectures are quickly becoming the dominant approach for building scalable, heterogeneous SoCs. By disaggregating a monolithic die into multiple interoperable chiplets, silicon designers gain flexibility in process node choices, reuse of proven functions, and faster time-to-market. At the same time, disaggregation breaks one of the most fundamental assumptions in traditional SoC sec... » read more

Securing UALink: Introducing A UALinkSec Security Module


By Dana Neustadter and Vincent van der Leest Over the next decade, artificial intelligence will dominate computing, driving profound changes in both hardware and software architectures. This transformation will reshape data center design and interconnect technologies, creating new opportunities for innovation. As AI workloads scale, the need for high-speed, low-latency communication between ... » read more

Building Trust At The Silicon Level: Secure Storage Solution For OTP IP


As semiconductor designs advance into cutting-edge nodes, the complexity of integrated IP blocks from diverse sources is expanding the attack surface. Traditional software-only security measures are increasingly inadequate, as attackers exploit vulnerabilities beneath the software layer. To counter these risks, designers of AI accelerators, automotive domain controllers, aerospace systems, a... » read more

Navigating FIPS 140-3


FIPS 140‑3 is a U.S. federal standard. Validations are issued under the Cryptographic Module Validation Program (CMVP), jointly managed by the National Institute of Standards (NIST) and the Canadian Center for Cyber Security (CCCS). These validations are accepted by both U.S. and Canadian federal agencies. The standard imposes strict requirements on security boundaries, operational environmen... » read more

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