AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; memory test facility; Taiwan investments; SiC teamup; DRAM sizing; sequentially stacking silicon; MIPI A-PHY SerDes automotive compliance.
Panel-level packaging, hybrid bonding, new substrates, and fine-pitch interconnects topped the list of advanced packaging technologies at ECTC this week. Among the announcements:
Fig.1: ASE’s automated panel-level packaging line supports 310mm × 310mm format
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Semiconductor Engineering published the Systems and Design newsletter this week, including these top articles:
Plus:
Rambus introduced a complete DDR5 9600 client memory module chipset for high-performance CUDIMM, CQDIMM, and CSODIMM modules.
Intel announced a family of processors for handheld gaming systems and discussed the origins of the EMIB, Embedded Multi-die Interconnect Bridge.
Infineon released SECORA Connect X, a ready-to-integrate payment solution to help OEMs turn smart wearables — like smart rings, fitness trackers, and watches — into secure contactless payment devices.
Keysight added an executable whiteboard to its RF circuit simulation software that can capture simulations, optimizations, decision trees, and design parameters to generate structured data ready for AI workflows.
Siemens added geometric deep learning technology to its Simcenter engineering simulation and test solutions portfolio, enabling what-if exploration and the creation of efficient AI reduced-order models from CFD simulation data.
Adhesives company Lintec will produce carbon nanotube EUV pellicles at a new center within Japan’s National Institute of Advanced Industrial Science and Technology.
Georgia Tech researchers found that “NAND flash memory made with ferroelectric materials can withstand radiation levels up to 30 times higher than more conventional NAND flash memory. “
UIUC researchers created a low-temperature technique for stacking single-crystal silicon transistor layers into monolithic 3D chips, enabling dense vertical integration while staying within back-end thermal limits.
Monash University-led researchers created an on-chip programmable valley optoelectronic nanocircuit, integrating chirality-selective meta-waveguide photodetectors with TMDs.
Security standards consortium GlobalPlatform launched Pavona, an open-source silicon distribution for secure-by-default chip designs that includes certification-ready IP, two TSMC 3nm taped-out RoT reference designs, and what it calls the first openly available PQC stack for embedded silicon. Founding members of the project include Max Planck, Oxford, Qualcomm, and others.
Critical Factors For Storing Data In DRAM: New concerns and challenges for memory in AI data centers.
Steven Woo, fellow and distinguished inventor at Rambus, talks about latency under load, fill frequency, power issues, reliability, and cost considerations, and how all of these factors come together in HBM4 stacks.
Upcoming webinars are here, including:
How Data Rates Doubled, and Where Validation Reaches Its Limit, June 4
Be the SI/PI Expert: Route Correctly the First Time, June 17
Find upcoming chip industry events here, including:
| EVENTS | Date | Location |
|---|---|---|
| Electronic Components and Technology Conference (ECTC) | May 26 – 29 | Orlando, Florida |
| Hardwear.io Security Trainings and Conference USA | May 26 – 30 | Santa Clara, CA |
| COMPUTEX Taipei | Jun 2 – 5 | Taipei |
| Siemens EDA IC Forum Europe | Jun 3 – 17 | Copenhagen June 3; Munich June 9; Dresden June 16; Eindhoven June 17 |
| SWTest Conference | Jun 8 – 10 | Carlsbad, CA |
| Hardware Pioneer Max | Jun 10 – 11 | London |
| ESD Alliance 2026 Executive Outlook: How Agentic AI Will Change Chip Design and Verification | Jun 10 | San Jose, CA |
| IEEE/JSAP Symposium on VLSI Technology and Circuits | Jun 14 – 18 | Honolulu + Virtual |
| Automotive Electronics Congress | Jun 16 – 17 | Ludwigsburg, Germany |
| 3D & Systems Summit | Jun 17 – 19 | Dresden |
| Scaling DRAM Technology to Meet Future Demands: System Challenges and Opportunities | Jun 27 | Raleigh, North Carolina |
| International Symposium on Computer Architecture (ISCA) | Jun 27 – Jul 1 | Raleigh, North Carolina |
| ALD/ALE 2026: Atomic Layer Deposition and Atomic Layer Etching | Jun 28 – Jul 1 | Tampa, Florida |
| International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD) | Jun 29 – Jul 2 | Dresden, Germany |
| The Chips to Systems Conference (DAC) | Jul 26 – 29 | Long Beach, CA |
| Find all events here. |
re: the pedigree of Intel EMIB & HBM LC
the technology for embedding dies into organic substrates was ready long before the need for EMIB arose around 2013 to boost wide I/O HBM Memory to CPU interconnect density
Around 2002 the Substrates group at Intel Chandler, AZ ( ably supported by Intel KK i,e. Japan ) had started R&D to embed dies into Build Up type Organic substrates . The motivation was lowering the Parasitics of power delivery to the X sistors ( ultimately to improve Clock Rate ), NOT merely boost interconnect densities ( early EMIB, but now – T is getting WARM, creeping back to the original 2002 objectives ) a current concern.
HVM for the current major version of BU type Organic Substrates ( Cu lines by Semi Additive Plating, NOT by subtractive etching, unlike the original IBM Japan SLC process limited by yield loss to L/S > 35 um ) w/ L / S of 20 um started at Intel ( OLGA ) in 1998 @ 2 mn pcs / wk ( by 2002 IBM Japan too changed to the Intel SAP process ( but by the IBM Japan had become Kyocera ). The Intel SAP process for BU Organic Substrates ( OLGA ) still in HVM today 28 yrs later ( now 8 / 8 um on larger Panels ), itself was descended from the SAP process for Electroplated Flip Chip Wafer Bumping ( another improvement over IBM and its Evaporated C4 ) developed at Motorola around 1991
The strategy for using Si Bridge Chips to assemble MCMs was already used ( & Patented ) by1991 in neighboring Motorola ( Tempe, AZ ) in an INVERSE Flip Chip configuration ( to implement a Heat Extraction from MCMs of HOT Bipolar ASICs for Supercomputers ) , mechanically far simpler than IBM TCM, once the Digital Camera guided FC Assy. Robots pioneered at Motorola were ready also by 1991.
HBM could not have been possible w/o the u Pillar FC also invented and put into HVM at Motorola by 1996 using Robotic Assy. lines. Today EEs ( IMEC ) not conversant w/ Metallurgy ( key to Adv. Packaging ) or responsible for costs might salivate about the Partitioning prospects of HBCu but what about the Yields ? Where is GraphCore today for who TSMC had by 2022 partitioned the Power Dely. Passives and interconnected them to Logic by HBCu ?
Last year AI Module makers had to spend $ 36 bn for HB, almost as much as their in house GPU. CPU,…. and they are going to have to spend 30% higher this year due to LOW yields for HBM 4 that has just started to Ship !!
But a solution is just around the corner, HBM – n ( where n = 4,5, .. ) – LC ( Low Cost ), 30% higher Die utilization, 30% higher Stacking Yield, perhaps 50% cheaper than HBM 4 ( on a per GB the price differential for which is 5x over LP DDR 5X ) !
Innovations for Adv. Packaging today require just as much Theory & Mathematical Optimization as was the case in 1990 when it was pioneered at Motorola in AZ.
And this time around siphoning off of all the AZ developed technologies will NOT be quite so easy, even though the clueless US Govt. ( e.g. CHIPS in DC ) has attracted them to AZ.
sd/
Dr. Dev Gupta
Chair IEEE – IRDS PI