CPO Is Extending The Limits Of What’s Possible In AI Data Centers

Key Takeaways

• I/O architecture must be co-designed with compute from day one.
• Partitioning SoCs into heterogeneous chiplets (compute, EIC, PIC, lasers) directly affects power delivery, floor-planning, interconnect topology, and system scalability.
• Successful CPO designs require architects to think in multi-physics terms, balancing electrical signaling, thermal stability, optical behavior, and mechanical constraints at the package/system level.

AI data centers are starting to replace copper with co-packaged optics in an effort to reduce energy consumed per bit and increase bandwidth.

The advantage of using CPO is that it positions optical connections much closer to the ASIC, GPU, or CPU, reducing the need for long and inefficient electrical traces. And while it’s not inherently low power, CPO offers extremely low energy consumption per transmitted bit — a crucial metric for data center efficiency.

Instead of using traditional, distant pluggable transceivers, CPO integrates photonic engines directly onto the same package substrate, or within the same module, allowing electrical signals to travel only a few millimeters in a multi-die assembly, rather than the usual 15 to 30cm across a PCB from the chip to the front panel.

This is an important puzzle piece for AI. According to McKinsey & Company, meeting global AI demand will require $5.2 trillion in data center investments by 2030. Therefore, solving the power and bandwidth challenges is crucial to ensure hyperscale companies achieve the best return on investment. Leading the pack on CPO adoption are Broadcom, Nvidia, Intel, Marvell, and Ayar Labs, with a variety of technologies and products, enabled by such foundries as GlobalFoundries, IBM, Intel Foundry, Tower Semi, and TSMC. EDA tool suppliers Cadence, Keysight EDA, Siemens EDA, and Synopsys have stepped up with CPO tools, as well.

“Hyperscalers are leading the way in driving the changes we are seeing,” observed Tony Mastroianni, senior director 3D IC solutions engineering at Siemens EDA. “Heterogeneous integration allows us to move beyond the limits of Moore’s Law. Although we’ve been using silicon interposers for over a decade, their size is restricted. However, new organic and glass interposers are emerging, enabling full panel-sized substrates that can accommodate enormous amounts of silicon, even up to a meter by a meter. The demand for AI has intensified the need for performance, with efficiency often taking a back seat. Achieving such performance now requires immense power, comparable to nuclear reactors, making energy consumption a critical challenge. I/O bandwidth is another major issue, and these are precisely the problems that CPO addresses effectively.”

Others agree. “Co-packaged optics are chosen for their high bandwidth and low power per bit, though they aren’t necessarily low-power technologies overall,” said Marc Swinnen, senior director of product marketing at Synopsys. “Lasers are hardware-efficient, but ring resonators require constant heating via small heaters to maintain the photonics IC’s temperature. While the total power isn’t low, the energy per bit is (measured in picojoules), making it efficient when considering bandwidth.”

Fig. 1: Simulated ring resonator. Source: Synopsys

The fundamentals of CPO
For the chip architects and engineers, there are many aspects to CPO.

“Anybody who’s looking at the system architecture — the entire system — in a data transmission needs to think about what type of technology they’re going to use based on the other important considerations,” noted Hee-Soo Lee, high-speed digital design segment lead at Keysight EDA. “For example, bits per joule is how much energy you’re consuming to produce one bit of data transmission. AI data centers are power hungry, so going to low power is very challenging because you are consuming a lot of electrical current. For customers designing compute nodes for AI data centers, a single two-inch-square chip can draw nearly 35,000 amps. Given that voltage, the power consumption is enormous — up to 35 kilowatts per chip. Managing this level of power is a significant challenge in advanced package design, including but not limited to CPO. With potentially millions of such chips, supporting their energy needs may require building dedicated power plants, as existing solutions are insufficient.”

DSP chips are among the most power-intensive components in a system, so designers often try to minimize their use. “This shift is motivating people to explore CPO, which allows direct conversion to optics rather than relying on traditional DSPs or ASICs, resulting in greater efficiency,” Lee said. “From a system architect’s perspective, this creates challenges since chip design must now consider both electrical and optical factors. There is growing interest in EO, OE, and eOe systems, meaning conversions between electrical and optical signals. Ultimately, these developments are driven by the insatiable power demands of AI data centers, making the transition toward more efficient solutions understandable.”

At the same time, there are a number of concerns regarding the power needed to drive signals between the EIC and the PIC. “These systems require specialized voltage-controlled circuits to drive current into the rings, generating heat as a result,” noted Lang Lin, principal product manager at Synopsys. “This process essentially involves applying power to induce temperature changes, which can demand significant energy. Each ring may consume approximately one to ten milliwatts of power. While current systems might utilize around sixty-four rings, there are reports — such as from DARPA programs — discussing the integration of thousands of rings in future designs. Scaling up photonic circuits to this extent would approach levels seen in transistor counts today, potentially reaching hundreds or even thousands of rings.”

Supplying power to these rings becomes a significant challenge. “For example, powering 1,000 rings at 1 milliwatt each would require about 1 watt overall,” Lin said. “Additional circuitry, such as EICs (electronic integrated circuits) with numerous amplifiers, further increases power consumption, as do supporting components like GPUs and CPUs, whose power demands remain substantial. I/O power is also considerable due to high data transfer rates, potentially accounting for 50% or more of total power usage. As systems continue to scale, ensuring adequate power delivery will remain a critical concern.”

Compared to interconnected copper bases, the size is much smaller, but power delivery remains a challenge. “Traditionally, voltage regulators were placed on the package or PCB, but now it’s common to integrate them onto a die as IVRs (integrated voltage regulators). Multiple IVRs may be needed for various power domains with different voltages, such as circuits, photonics, and electrical components. As a result, this complex system presents significant challenges in power delivery,” Lin said.

CPO mechanics
The CPO approach utilizes two chips — a photonic device positioned at the bottom and mounted directly on the substrate, with a mini SerDes stacked on top, forming a 3D chiplet configuration.

“This assembly is physically attached to an interposer, which may be silicon, but is typically used for larger substrates due to increased wiring requirements, whereby the fiber connects directly to the photonic device within the package, representing the essence of CPO,” Siemens’ Mastroianni said. “By integrating the fiber in this manner, power issues are effectively addressed, allowing the SerDes to communicate efficiently with the chiplet. Although it might seem logical to place the SerDes at the bottom, since it communicates with the chiplet, mechanical constraints require the photonics to sit on the substrate. The SerDes positioned above transmits signals through the photonic device using TSVs, facilitating communication across the substrate, similar to a silicon interposer. Alternative interposers, such as organic bridges or glass, also offer interesting possibilities.”

Fig. 2: Location of optical waveguides in multi-die assemblies. Source: Siemens EDA/Chiplet Summit

While the CPO design achieves significant reductions in I/O power on the chip, transistor processing power remains unchanged. “Previous solutions like HBM have addressed memory power I/O concerns, and CPO now tackles the power and bandwidth challenges associated with I/O. Data exits the chip through multiple channels, typically 8 to 16 within the fiber, delivering exceptional bandwidth with low power consumption. A laser source is required, and ongoing research aims to integrate it onto the chip itself. Additionally, CPO alleviates traditional SerDes congestion by eliminating the need for numerous package pins, thereby freeing up bumps for power delivery, including backside delivery. While not universally applicable, this solution represents a significant advancement, particularly for hyperscalers constructing mega chips,” he said.

CPO design challenges
CPO extends beyond traditional electrical-only boundaries, integrating optical components directly with high-performance ASICs, CPUs, or GPUs. That, in turn, requires a specialized opto-electronic design approach to manage the physical and functional convergence of light and electricity in a single package.

For the chip architect and designers, there are a number of areas in which skills must be up-leveled:

• Heterogeneous chiplet integration. Designers will need to use a chiplet-based architecture to create smaller, specialized dies for compute, memory, and photonics. Advanced packaging like TSMC’s COUPE or Intel’s Foveros will be used to interconnect these different materials within one system.
• Eliminating signal bottlenecks. Since the photonic engine is placed directly beside the ASIC, long lossy copper traces are eliminated, which could save up to 30% of total system power.
• Thermal-optical co-design. Photonic components are highly temperature-sensitive, so the design team must perform complex multi-physics simulations to manage heat flow from high-wattage compute dies so it doesn’t cause wavelength drift or alignment errors in the optics.
• Silicon photonics development. Designers will need to create photonic integrated circuits (PICs) that serve to integrate modulators, detectors, and waveguides onto silicon substrates using standard CMOS fabrication techniques.
• Laser source management. Architects and designers must decide whether to integrate the laser directly on-chip or keep it external. Designers can opt for redundant laser design or integrated monitoring to ensure reliability, as lasers are typically the least reliable component in the stack.

In all of this, chiplets/multi-die design will play a giant role as SoCs are partitioned into multiple smaller dies that are integrated into a single package. “The combination of dies fabricated using different process nodes within a single package, also known as heterogeneous integration, enables optimization of both cost and power consumption,” said Raj Pugo, NPI packaging manager at Presto Engineering. “A pluggable transceiver is a module that enables the conversion of electrical signals into optical signals, and vice versa. It typically consists of a transimpedance amplifier (TIA), driver, laser, and photodiode. The integration of these components forms the optical engine (OE). CPO refers to the integration of a GPU or ASIC together with all the components of the optical engine within a single package. In other words, CPO is the heterogeneous integration of compute chips (GPU/ASIC) and optical engine components (OE) into a single package.”

CPO challenges and progress
CPO adds a whole slate of multi-physics challenges. Photonics signals can drift due to changes in temperature, and materials can directly affect light propagation. Waveguides can have irregularities that are roughly equivalent to line-edge roughness for electronic signals. And all of this needs to be addressed together with the rest of the system design rather than in isolation.

Fig. 3: Simulating an optical waveguide. Source: Synopsys

“We need all our tools to work together, using thermal stress warping profiles and fitting them into optical circuit performance simulations,” said Synopsys’ Lin. “Previously, this relied solely on empirical data, but now our simulations are tied directly to real system measurements.”

This integration is necessary because, in simulations, it’s important to distinguish between troublesome effects and those that can be ignored. Sometimes an overlooked effect has more impact than expected and should be included in the modeling process.

This is where large EDA companies are turning their attention. Among the developments:

• Cadence is collaborating with photonic supercomputer developer Lightmatter to develop CPO solutions that integrate Cadence’s high-speed SerDes IP with Lightmatter’s optical engine. The companies are focusing on integration with advanced-node CMOS technology and standard packaging workflows to pave the way for high-performance, manufacturing-ready CPO in next-generation AI and HPC environments. Cadence also collaborated with Tower Semiconductor to create a heterogeneous integration flow that supports die-to-wafer and wafer-to-wafer applications for PIC/EIC sub-systems using Tower technology.
• Keysight EDA completed its acquisition of Synopsys’ optical solutions group in October 2025, integrating advanced optical simulation tools into Keysight’s existing EDA tools. Subsequently, Keysight EDA released a software tool for chiplet and 3D-IC designs for simulation and validation of co-packaged photonics and electronics.
• Siemens EDA recently acquired Canopus AI to enable the integration of AI-driven metrology and inspection into its EDA portfolio, which directly impacts CPO manufacturing by improving the precision and yield of complex photonic integrated circuits (PICs). And in January, Siemens expanded its partnership with Nvidia to integrate GPU acceleration across its EDA tools, specifically targeting verification and layout optimization for the high-density interconnects required by CPO.
• Synopsys is collaborating with Lightmatter, and the two companies are working to optimize the electrical-to-optical interface. Synopsys continues to collaborate with TSMC and has extended its partnership with Nvidia to accelerate optical simulation and engineering workflows using Nvidia’s GPU-accelerated computing.

Next steps for CPO
For CPO to go more mainstream, some advanced packaging issues need to be worked out.

“CPO offers higher bandwidth density, lower power consumption, and reduced latency compared with conventional packaging approaches, making it critical for next-generation AI solutions,” noted Presto’s Pugo. “2.5D packaging forms the foundation of CPO, enabling the integration of photonic ICs and electronic ICs alongside GPUs or ASICs. The main challenges include heat dissipation near the GPU/ASIC (advanced heat management such as liquid-cooled cold plates, microfluidics, microchannel heat sink), achieving higher-precision optical coupling, improving laser reliability, increasing manufacturing yield, and reducing manufacturing costs. Additional challenges involve promoting the standardization of CPO module form factors, improving the automation of testing and validation, and ensuring the serviceability of the optical engine (OE) in the event of failure. Addressing these challenges will enable the broader adoption of CPO across the industry.”

Then, from a physics perspective, examining the packaging reveals a complex information flow. “Data arrives via a fiber optic cable, which connects to a microlens that focuses the light onto a photonic integrated circuit (PIC) equipped with a grating,” Synopsys’ Swinnen said. “The grating converts the incoming light into electrical signals, after which the PIC performs preliminary processing of these signals. At this stage, the PIC works in tandem with an EIC. The microlens directs the light to the PIC, where it is processed, converted to electricity, and subsequently transferred to the EIC for further electronic processing. This interface then connects to external systems, completing the information pathway.

The refractive index of waveguides in photonic ICs is highly sensitive to temperature, which affects performance. “To manage this, the system is heated to a stable high temperature — around 100 degrees — so minor heat fluctuations become negligible. Heaters are built in to maintain this stability, but heat still dissipates through the electronic ICs, making thermal management essential,” Swinnen said.

The system‑integration is impacted, as well, because the photonic circuit, constructed from optical links, is highly sensitive to temperature changes. It is therefore necessary to design a multi-die CPO to ensure that all elements function within their appropriate temperature ranges without excessive coupling.

Conclusion
For very large AI mega chips, power and bandwidth — not compute — are now the limiting factors. Traditional high-speed electrical SerDes are extremely power‑hungry because data has to travel off-package and across boards. CPO addresses this directly by replacing long electrical paths with optical ones inside the package. In doing so, photonic devices are integrated alongside compute silicon, which allows data to leave the chip optically almost immediately, cutting I/O energy by orders of magnitude while delivering massive bandwidth. At the same time, that frees up packaging resources by eliminating large numbers of high-speed electrical I/O pins, reduces congestion, allows more bumps to be dedicated to power delivery, and enables advanced approaches like backside power delivery.

Additionally, thermal and mechanical challenges exist but are manageable. While photonic devices are sensitive to temperature and potentially stress, the issue is not raw heat generation but temperature stability. These challenges can be addressed through design techniques such as temperature control loops, careful floor-planning, and stress-aware packaging, which make CPO feasible. And while CPO is not for all chips today, it is almost essential for large, high-I/O AI systems, where it fundamentally changes what is possible by making otherwise unmanageable power and bandwidth requirements tractable.

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