tag: Keysight EDA

An AI Model Fit For Purpose
By Brian Bailey - 09 Jul, 2026 - Comments: 0

Key takeaways A model can only be used for its intended purpose, in a defined context, without taking unknown risks.  Models must be created using a well-defined process and verified in a way that provides a level of independence.  Deployment requires trust and a way to track the properties of the model. A model captures some kind of behavior exhibited in the real world, b... » read more

AI Data Centers And Auto Industry Converge On Same Issues
By Liz Allan - 02 Jul, 2026 - Comments: 0

Key Takeaways:   AI data centers need power from a range of sources, including batteries, to safeguard against blackouts, transient voltage spikes, and grid demand spikes.  As with regenerative braking and bidirectional charging in electric vehicles, data centers could feed power or heat back into the grid for public use, but the immediate goal is to disrupt the grid as little as pos... » read more

Observability Is A Missing Layer In AI-Era Chiplet Design
By Ann Mutschler - 01 Jul, 2026 - Comments: 0

Key Takeaways: In chiplet-based architectures, observability must be designed as a fabric-aligned, cross-die telemetry plane so architects can correlate traffic, latency, congestion, and fault behavior across package boundaries without losing system context. AI can extract value from high-volume silicon telemetry only when the architecture provides consistent instrumentation, near-senso... » read more

Rethinking Chip Verification
By Ann Mutschler - 29 Jun, 2026 - Comments: 0

Key Takeaways: AI and modern tools are easing traditional verification pain, but they're not addressing the underlying bottleneck in complex designs. Work is underway to create a golden, unambiguous spec above RTL, tracing requirements from spec to implementation to verification and checking for gaps, conflicts, and inconsistencies across levels and blocks, often with AI help. Tool c... » read more

I/O Design Challenges Grow In AI Data Centers And HPC Clusters
By Liz Allan - 25 Jun, 2026 - Comments: 0

Key Takeaways: A designer’s choice of I/O connectors and interconnect protocols can be the difference between a massively profitable AI chip and a flop. I/O tradeoffs impact airflow, cooling, rack design, power coming into the rack, and other critical aspects of HPC chip design. Reliability is paramount, so standards must be followed, and I/Os need redundant pins. Other innovations... » read more

Designing Chips That Can Explain Themselves
By Ann Mutschler - 17 Jun, 2026 - Comments: 1

Key Takeaways: On-die telemetry gives architects a path to replace worst-case design margin with measured silicon behavior, improving PPA without compromising resilience. As monitor density and control-loop speed increase, observability must be architected hierarchically across local hardware response, on-die processing, and fleet-level learning. The real payoff is architectural: str... » read more

Keeping Security Algorithms Current Is Getting Harder
By Ann Mutschler - 04 Jun, 2026 - Comments: 0

Key Takeaways: Keeping security algorithms current is now a lifecycle challenge that spans chip design, manufacturing, deployment, and long-term maintenance across the supply chain. To stay ahead of emerging threats — especially post-quantum risks — hardware must be built with cryptographic agility, secure roots of trust, and reliable update mechanisms from the start. The bigge... » read more

Toward Agentic Verification
By Brian Bailey - 28 May, 2026 - Comments: 1

Key Takeaways: Agentic verification provides flow orchestration for common repetitive tasks. Capabilities will expand when tools can learn from a larger context, including the specification. Design houses need to fully understand the costs and benefits and plan accordingly. Agentic verification is more than a buzzword. It is a pivotal moment in the evolution of verification ... » read more

Observability Is Essential For Modern Silicon
By Ann Mutschler - 28 May, 2026 - Comments: 0

Experts At The Table: In-silicon observability — also known as on-die or on-chip visibility — is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor Engineering sat down to discuss this with Andy Nightingale, vice president of product management and marketing at Arteris; Nandan Nayampally, chief commerc... » read more

Chiplets Need A New Workflow
By Ann Mutschler - 14 May, 2026 - Comments: 0

Key Takeaways: Chiplet design turns semiconductor development into a system-level problem, requiring coordinated workflows across design, packaging, verification, test, and reliability. Successful chiplet workflows must handle multi-physics challenges — especially thermal, mechanical, power, and signal integrity — early enough to reduce costly failures before assembly and tape-out. ... » read more

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