Deep vertical holes and re-entrant features challenge the best metrology methods.
Each generation of 3D NAND packs about 30% more bits than the previous version, with current devices storing up to 2 terabits of data in a die the size of a fingernail. With new product introductions shrinking from 18 months to every 12 months, chipmakers are constantly innovating to enable this prodigious scaling pace.
3D NAND technology is a core ingredient in mobile phones, solid-state drives, data centers, PCs and SD cards. Over 30% of capital equipment orders each year go toward toolsets for building flash chips. In addition to its important role in global spending, 3D NAND drives 3D metrology and inspection technology to new extremes. This requires a combination of technologies, including optical, X-ray, high-landing-energy e-beam and e-beam voltage contrast, while brand new methods such as GaN-based e-beam are being introduced for their ability to detect critical defects.
Scaling bit density
Ever since 3D NAND started playing a role in enterprise-grade solid-state drives, chipmakers have been using gate-all-around charge-trap cells. Those are somewhat similar to floating-gate cells, but with different voltage patterns moving electrons in and out of the trapping layer. Silicon nitride forms the trap cells.
Silicon nitride is a good choice for isolation because it is less susceptible to defects and leakage than polysilicon, and it requires lower voltage to support program/erase cycles. Because of this, the charge-trap cell can use a thinner oxide layer and reduce stress on the layer, which results in higher endurance rates than with floating gate cells. The charge-trap approach also enables faster read and write operations and consumes less energy. [2]
To fabricate 3D NAND devices, chipmakers deposit multiple horizontal film layers of memory cells, into which vertical channel hole connections are made. To increase memory capacity, more but thinner films of oxide-nitride are stacked in 2 or 3 tiers. Cryogenic etching systems, offered by Lam Research and TEL, play a critical role in producing high-aspect-ratio holes <100nm in diameter and 6 to 10 microns deep, because at ultra-low temperatures (down to -60°C), etch rates are substantially faster because reactive species have higher concentration and removal capability at the etch front. An amorphous carbon hard mask aids the vertical etch. Challenges include preventing bowing, twisting, or tilting while achieving near-vertical profiles.
The scaling of 3D NAND is progressing on three fronts. First, NAND manufacturers are scaling the pitch between contact holes, enabling a greater number of memory cells in the same silicon footprint. Second, stacks are growing vertically by adding more layers and tiers of oxide/word lines. Third is the so-called logical scaling. Here, more bits are packed into each cell, moving from triple-level cells to quad-level cells and penta-level cells (TLC, QLC and PLC, respectively), each operating at different threshold voltages.
The combination of horizontal and vertical scaling requires absolute profile control from the etching process. “If the hole size and hole shape are not perfect, you will have interference from nearby devices so that logical scaling will not be possible,” said Tae Won Kim, corporate vice president of global products at Lam Research.
Among all the important features in 3D NAND (see figure 1), including memory holes, slits, staircase contacts, and peripheral contacts, the vertical memory holes are the smallest. “Customers want high-resolution z-profiles of channel holes, wordline cut trenches and hard mask holes,” said Nick Keller, director of applications development, optical metrology at Onto Innovation. “There are also steps where they want to know the vertical recess in etch back steps that occur at the bottom of the channel holes (or at the very top).”
Fig. 1: Key features in 3D NAND include tiny memory holes, slits, staircase contacts, and peripheral contacts. Source: Lam Research
Stacking cells vertically has several important benefits. It provides a higher bit density and improves electrical performance by shortening the interconnect length between cells, which in turn reduces power consumption. The nitride layers are sacrificial, so they are removed using a wet etch and then replaced with metal.
With the gate-last integration, the word line is formed using tungsten. The tungsten replacement and separation processes can create several defect types, including tungsten voids, oxide voids, and bridging defects.
The integration of the word line is a particular challenge for process integrators and for defect inspection and reduction. Techniques like CD-SEM or atomic force microscopy (AFM) have a difficult time seeing inside features. The main defects of interest are typically sub-surface (especially voids) in the stack, or defects caused by residue after etching at the bottom of high-aspect-ratio memory holes.
Another key metrology step follows the tungsten etch or the tungsten recess step. This juncture is critical because under-etch of the tungsten can lead to word-line shorting and destruction of the memory string. Over-etching typically causes degradation in device performance.
Once the memory cell stacks are fabricated, they are connected to the control logic below using wafer bonding in the latest 3D NAND chips. Acoustic microscopy is a common method used to detect voids at the critical wafer-wafer interface.
The best tool for the job
Scatterometry, also known as optical CD (OCD), is widely used throughout fabs. Years ago, these techniques were extended from the visible into the infrared wavelengths to enable better measurement inside vertical holes.
“For 3D NAND, IRCD has been proven in HVM for the high-aspect-ratio z-profile measurements,” said Keller. He noted that while critical dimension small-angle x-ray scattering (CD-SAXS) also has been proven in manufacturing settings, especially for tilt and overlay measurements between strings (tiers), the throughput of CD-SAXS cannot compete with that of optical methods. So it may be that CD-SAXS is employed selectively in areas where other methods cannot provide the same information, such as ensuring good overlay from one memory hole tier to another.
Infrared critical dimension metrology (IRCD) offers vertical profile sensitivity simply due to the wavelength range it operates in and the dielectric layers that are in the superlattice (silicon nitride and silicon dioxide). Like OCD, IRCD is an indirect measurement that relies on a Muller Matrix correlation of the spectral response to CD measurements. To meet the needs of high-volume manufacturing, IRCD needs to capture within-wafer CD variations, as well as wafer-to-wafer, at a processing speed comparable to that of OCD systems.
“Dielectric materials in the mid-wavelength and long-wavelength infrared ranges have absorption peaks that depend on the types of bonds found in the molecule (for SiO2, it would be the strong Si-O bond due to “stretching” around 1000cm-1). The absorption peaks have amplitude and width that vary with wavelength and therefore modulate the penetration depth of light,” explained Keller. “Second, compared to UV-VIS-NIR spectroscopic instruments, creating an OCD model in the IR is faster due to fewer high-frequency oscillations, which is computationally advantageous because less harmonics are required in the RCWA (rigorous coupled wave analysis) calculation.”
IRCD can be used to measure channel hole CD and the silicon nitride recess on first- and second-tier channel holes. Measuring the nitride recess is critical because confinement in self-aligned charge trap layers helps improve data retention in the memory device by preventing lateral charge migration.
A fundamental challenge with extending existing tools to measure critical dimensions in deep features is the signal absorption by the thin films on the side. “If the film layers have no absorption, there is no theoretical limit, but modeling can become challenging due to loss of spectral resolution or parameter correlation,” said Keller.
E-beams and X-rays
Electron-beam tools, in general, provide a more detailed review of defects identified using optical systems. In recent years, Applied Materials and KLA have developed high landing energy systems to zoom into high-aspect-ratio holes.
E-beam metrology with high landing energy in the 30keV region can penetrate high AR holes. Detection of both backscattered and secondary electrons can identify defects of interest several microns deep. High landing energy e-beam can indicate conditions of remaining tungsten in memory holes. Deep learning helps the defect classification process during ADC runs, while also discriminating between nuisance defects and killer defects.
The high-landing-energy e-beam system from Applied Materials uses a cold field emission gun to deliver more electrons to the structure in a narrower beam. This tool can provide up to 60keV landing energy.
But chipmakers are exercising caution in the use of high landing energy e-beam, because ionizing radiation can induce damage in sensitive NAND layers — especially the dielectric stacks. Any inadvertent change to the charge-trap region can affect the device threshold voltages, degrading performance or long-term reliability.
Voltage-contrast inspection with an e-beam point-scan system provides an effective means of identifying critical hot spots. This method is often applied during the device learning or ramping stages when hot spots are extremely rare but present.
“When people say, ‘I want to look at a hot spot,’ they’re thinking it’s something you can look at — one or two of them — and see the problem. But stochastic defects have both a deterministic element and a statistical element,” said John Kibarian, president and CEO of PDF Solutions. “So the reality is, I‘ve got to look at 10 or 20 billion of them to see just one that fails. That hot spot has a failure rate that is above the floor level, but it’s still very, very infrequent. And that’s the mining you’re looking for with hot spots these days.”
Software plays a key role in ferreting out these hot spots. “That’s really the challenge — identifying where to look in the e-beam tool to give you that ability to look at tens of billions of spots in a reasonable amount of time,” Kibarian said.
Yet another e-beam technique with an alternative source may prove useful in identifying NAND defects. Kioxa recently announced that it is evaluating a GaN-based e-beam tool for defect inspection in 3D NAND applications. [3] Jointly developed by Nagoya University’s Amano-Honda laboratory and Photo Electron Soul, a start-up firm, the GaN e-beam system promises non-contact defect inspection, electrical inspection, and profile measurements. The system uses selective e-beam radiation and real-time control of beam intensity to minimize any beam misalignment to enhance defect detection and root-cause analysis of failures.
Another promising option for seeing defects inside high AR holes are X-ray methods including X-ray CT (computed tomography). X-ray inspection in general benefits from recent improvements in X-ray source and detection methods. “With the change to gate-all-around [structures], there is this increased need for metrology,” said Juliette van der Meer, product marketing manager at Bruker. “We met it with the launch of a new X-ray tool with increased source power and a better detector to keep up with the needs in high-volume manufacturing.”
Finally, after the memory cell structure is built, NAND chipmakers will bond the “CMOS under array” chip to the NAND memory cells. Here, acoustic microscopy is proving useful in identifying small voids between wafers bonded in a hybrid or fusion bonding process.
Acoustic microscopy, which sends a high-frequency signal through a water medium, identifies defects in bonded wafers. One approach taken by Nordson Test & Measurement involves spinning the wafer at high speed while using a waterfall transducer to provide non-immersion scanning, minimizing the risk of contamination or false-bond indications. The transducer type (frequency) is chosen based on the application, providing a range of focal lengths for detecting voids in bonded wafer or bonded chip-on-wafer applications.
Ground truth verification
While all the above methods are non-destructive in nature, destructive approaches enable device cross-sectioning using focused ion beam milling coupled with a scanning electron microscope (FIB-SEM) to view actual cross-sections of device wafers. During process development and ramping, FIB-SEM methods can reveal incomplete etching of features, bowing, or twisting, and especially channel hole-to-channel hole variations.
Process modeling/virtual metrology
The growing challenge behind characterizing many of the subtle and complicated yield-limiting factors of severely scaled features is making virtual wafer fabrication, process modeling, and virtual metrology increasingly attractive. The combination can help identify the best metrology sampling rate as a device enters production. Chipmakers can evaluate tradeoffs between metrology precision and speed of measurements. Virtual fabrication also has the potential to accelerate the semiconductor development cycle by substituting limited and lengthy wafer-based design-of-experiments with fast, large-scale virtual DOEs.
Engineers from Coventor, a Lam Research company, quantified the extent of hole CD variation and channel taper from the top of the channel to the bottom using virtual process modeling and metrology. [4] They modeled a stack of alternating layers of oxide/nitride and calculated the channel area at the top and bottom of the channel as a function of the high-aspect-ratio etch process.
“For a nominal etch condition, the CD variation from the top to the bottom of the channel can readily be seen and numerically quantified. To ensure that the channel etch reaches the bottom contact, the sidewall angle for each stack layer must be >88°, or the etch does not reach the bottom of the channel. By incorporating this type of virtual metrology and statistical process variation, the process boundaries of various channel etch process parameters can be optimized prior to running excessive trial-and-error silicon wafers,” stated the authors.
Conclusion
3D NAND devices push the envelope in metrology measurements and inspection of defects. With its abundance of high-aspect-ratio holes and challenging etch processes, chipmakers employ a combination of IRCD, X-ray inspection, e-beam methods with high landing energies, and e-beam voltage contrast to “see” inside deep features, looking for residues, incomplete etching processes, as well as bowing of features created by defects and non-vertical profiles.
As companies like Kioxa, Samsung, Micron and SK hynix prepare to roll out next-generation NAND with higher stacks, smaller slits, and smaller memory holes, it will take an all-hands-on-deck approach to reach yield entitlement across these complex memory arrays.
References
Related Reading
NAND Flash Targets 1,000 Layers
New techniques go beyond improved deposition and etching, but challenges stack up, too.
How Metrology Tools Stack Up In 3D NAND Devices
Buried features and re-entrant geometries drive application-specific metrology solutions.
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