Foundry rolls out aggressive new roadmap, focusing on area, power, and latency.
TSMC announced three new advanced process technologies at its North America Technology Symposium last week A13, A12 and N2U as part of its latest advanced technology roadmap.
Compared to the roadmap presented at last year’s tech symposium, the new roadmap shows the three new process technologies in gold text.
Figure 1: TSMC’s Advanced Technology Roadmap. Source: TSMC
To put these three into context, N2 is TSMC’s first node to use NanoFlex, and A16 will be TSMC’s first node to use Super Power Rail (SPR) backside power delivery technology. N2 is in production now, and TSMC claims that process has the strongest ever customer adoption, with more than 20 customer tape-outs received so far and over 70 in the pipeline. We expect to see N2 revenue showing up soon.
TSMC’s A14 uses its NanoFlex Pro technology and is targeted for 2028. A13 is a direct shrink of A14. It provides 6% area savings, and the design rules are fully backward compatible with A14. A13 is targeted for 2029, along with A12, which is an A14 platform enhancement with SPR. Figure 2, below, shows N2U’s incremental improvements over N2P and it is scheduled for production in 2028.
Figure 2: N2U Enhancement Advantages vs. N2P. Source: TSMC
Figure 3: PPA Comparisons From 2025 Tech Symposium. Source: TSMC
Figure 3 shows PPA comparisons from last year’s TSMC Tech Symposium. The A14 numbers were presented again this year without any changes. A16 had been advertised earlier for production in late 2026, but Figure 1 now shows it in 2027. The announcement of A12 for 2029 is an aggressive speedup in delivering a new technology node. TSMC also claimed that N2 is ramping better in terms of defect density reduction than N3. This is quite impressive, given that N3 is the last finFET node and N2 is the first NanoFlex node.
The demand for advanced packaging technologies is very high and largely driven by AI compute scaling requirements. TSMC is manufacturing the world’s largest 5.5-reticle size CoWoS, with > 98% yield in 2026. Figure 4 shows the roadmap for CoWoS and SoW support out to 2029, with an SoW-X projected to accommodate 64 HBM stacks. If we expect 64GB HBM stacks for 2029, that will imply a total of 4TB of HBM on an SoW-X.
Figure 4: TSMC CoWos and SoW Integration Roadmap. Source: TSMC
Another important technology to enable system scaling for AI is co-packaged optics. TSMC’s Compact Universal Photonics Engine (COUPE) is bringing optical signaling closer to the chip, and along with it come improved energy efficiency and latency reduction. Figure 5, below, shows the roadmap progression for CPO with COUPE.
Figure 5: Co-Packaged Optics Roadmap Using COUPE. Source: TSMC
TSMC also had its first quarter of 2026 earnings call on April 16. Figures 6 through 10 below show the dramatic impact that AI/HPC has had on revenue, and how it has displaced smartphones as the top revenue generator for TSMC. Figure 10 also shows how consistent the revenue percentages for N7, N5 and N3 have been for the last 6 quarters. It will be interesting to see how N2 will still start to impact these percentages moving forward as more finished wafers are delivered.
Figure 6: Revenue by Platform. Source: TSMC
Figure 7: Revenue by Technology. Source: TSMC
Figure 8: Historical Percent Wafer Revenue by Node Per Calendar Quarter (19 Years). Source: TSMC
Figure 9: Percent Wafer Revenue by Node Per Calendar Quarter (8 Years, N7 and Below Era). Source: TSMC
Figure 10: Percent Wafer Revenue for </= 7nm by Calendar Quarter. Source: TSMC
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