Oxides Bring Low Leakage Transistors To Leading-Edge Memories

AI workloads need to position more memory that uses less power in ever-closer proximity to computational logic. That overriding imperative is driving new memory designs and new materials exploration across a wide range of applications, including cache memory, working memory, as well as a new category, non-volatile memory used for direct computation.

The largest of these, by volume, is working memory. Despite extensive development efforts focused on resistive RAM and other novel devices, DRAM remains the technology of choice for most applications — so much so that the DRAM requirements of AI data centers are driving industry-wide shortages.

At the same time, DRAM scaling is becoming increasingly challenging. Designers hope vertical structures will enable them to increase density while avoiding the expensive lithography needed for continued pitch scaling. They also would like to use low-leakage transistors to reduce the refresh power demands of large memory arrays.

Amorphous oxide semiconductors like IGZO (indium gallium zinc oxide) offer acceptable carrier mobility with very low leakage. Amorphous oxides are especially attractive for stacked devices because they are easier and less expensive to deposit than epitaxial silicon/SiGe layers.

In DRAM, less leakage reduces refresh power
Unfortunately, while the low-temperature processes used to deposit oxide semiconductors are ideal for BEOL integration with CMOS, they tend to deteriorate at the high temperatures needed for DRAM integration. In particular, molecular dynamics simulations by Kyooho Jung and colleagues at Samsung showed that zinc migration during IGZO annealing leads to uncoordinated indium sites, resulting in dangling bonds.[^⁠1]

Though zinc-free IGO films performed better, the Samsung researchers still saw high levels of oxygen vacancies after annealing, especially in oxygen-deficient conditions. Optimizing the electrode material reduced interfacial migration and oxygen loss at the source and drain electrodes. IGO devices with optimized electrodes remained stable even after annealing at over 550°C.

A second group, Hao Shi and colleagues at ChangXin Memory Technologies, initially observed complete failure — zero yield — of their IGZO devices during BEOL processing.[⁠2] They attributed the results to thermal degradation and hydrogen incorporation. They produced functional devices by optimizing the IGZO deposition process, reducing hydrogen in their BEOL processes, and lowering the process temperature. From there, the use of an oxidation-resistant interfacial layer at the source and drain contacts, along with improvements to the gate insulator, yielded a double-gated transistor with an on current of 60.9 μA/μm and a subthreshold swing of 80 mV/dec. This work used wafer bonding to place a multi-tiered stack of horizontal oxide semiconductor-based memory cells on top of a conventional CMOS wafer.

Alternatively, Mutsumi Okajima and colleagues at Kioxia demonstrated a 3D DRAM oxide channel replacement process that helped reduce thermal degradation (see figure 1).[^⁠3]

Fig. 1: 3D DRAM process borrows mature oxide/nitride stacking capability from NAND for lower-cost bit scaling, followed by IGZO replacement channel to reduce thermal degradation. Source: IEDM [3]

The Kioxia group first deposited a vertical silicon oxide/silicon nitride stack, then defined holes for vertical bit lines and recessed the SiN to form gate electrodes. The sacrificial material used as a spacer during word line and capacitor formation was removed and replaced with an IGZO channel to finish the device. The prototype memory cell demonstrated a high on-current of over 30 μA/cell with a gate length of 45nm. The excellent on/off ratio, better than 10¹³, makes this an excellent candidate for high-density, low-power memory applications.

Gain cells offer SRAM speed in a smaller footprint
Oxide semiconductors are also of interest for capacitor-less “gain cell” memories, a potential alternative to SRAMs. A gain cell stores the data bit in the gate capacitor of a “write” transistor, where a second “read” transistor reads it. Silicon’s speed is advantageous for the read transistor in this design, while the very low leakage of oxide semiconductors extends the retention time of the write transistor. Shuhan Liu, with colleagues at Stanford, Nvidia, and TSMC, built a 256×256 array with this hybrid design, achieving a 3.6x density advantage and a 15% energy reduction relative to high-density SRAM.[^⁠4]

Fig. 2: Circuit diagram for 2T0C gain cell memory element. Source: Katherine Derbyshire/Semiconductor Engineeering

Typical oxide semiconductor transistors introduce undesirable parasitic delays, though, due to overlap between the gate and the source and drain. Sunbin Deng, with a group at Georgia Institute of Technology, instead demonstrated a fully self-aligned design, with a gap ensuring adequate separation.[^⁠5] Their 3T0C design achieved a 10X improvement in retention relative to cells with overlapping transistors. This approach effectively doubled the capacity and reduced the energy-delay-area product by 75% to 80% relative to comparable SRAM cells.

Integrating transistor-based memories into the BEOL process requires a tradeoff between the speed and maturity of silicon technology and the simpler processes but lower performance of alternatives. Researchers at Japan’s Semiconductor Energy Laboratory attempted to close the gap by using crystalline, rather than amorphous, indium oxide. Their devices achieved 5-nanosecond read and write times, with a retention time of more than 3,600 seconds (1 hour).[^⁠6]

Computing in memory needs stable data
Compute-in-memory designs seek to solve the memory bandwidth problem by performing calculations in the memory array directly. Many demonstration projects have used analog memories, such as RRAMs, depending on Kirchoff’s Law to produce a sum. Among other limitations, these designs require analog-to-digital conversions, which increase design complexity and consume more power.

Instead, Junmo Lee and colleagues at Georgia Institute of Technology, in collaboration with TSMC, paired tungsten-doped In₂O₃ with ferroelectric hafnium zirconium oxide (HZO) to build non-volatile capacitor memory elements on top of wafers from a standard 40nm CMOS foundry process. The lower process temperatures needed for oxide semiconductors facilitate BEOL integration. Here, the devices achieved non-destructive read endurance of more than 10⁹ cycles, with better than 10⁴ second (2.78 hour) retention time.[^⁠7]

FeFET memories place a ferroelectric in series with a conventional gate dielectric, making the transistor’s on/off state non-volatile. FeFET memories with silicon channels are difficult to integrate into BEOL processes because of the thermal requirements of silicon deposition. Instead, Jung-Kyun Kim and other researchers at Samsung used IGZO as the channel material. After fabrication, they annealed the devices in oxygen, stabilizing the oxygen vacancy concentration in both the IGZO semiconductor and the HZO ferroelectric. The result was a large 1.6 V memory window with endurance exceeding 10¹² cycles.[⁠8]

Conclusion
Memory requirements for AI workloads are extremely diverse, including DRAM for working memory, SRAM cache memory, and potentially non-volatile compute-in-memory arrays. The combination of low-leakage and low-temperature processing that oxide semiconductors offer opens up many opportunities for these materials in high-density memory applications.

References

1. Kyooho Jung, et al., “Thermally Robust, Highly Reliable Amorphous Oxide Semiconductor Transistors for sub-10nm Cell-On-Peri Vertical Channel DRAM Transistors,” 2025 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 29.2
2. Hao Shi, et al., “High Performance and Robust Oxide-semiconductor Channel Transistor DRAM with Multi-tiered Architecture,” 2025 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 29.3
3. Mutsumi Okajima, et al., “Highly stackable Oxide-semiconductor Channel Transistor Technology for Future High-density and Low-power 3D DRAM,” 2025 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 29.1
4. Shuhan Liu, et al., “Gain Cell Memory Scalability to 5-nm and Beyond,” 2025 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 29.5
5. Sunbin Deng, et al., “Demonstration of 3T0C Gain Cells with Self-Aligned Oxide Transistors for Parasitic-Aware Design at Array-level,” 2025 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 29.6
6. T. Matsuzaki, et al., “Crystal Indium Oxide for 64-kbit 2T0C Memory with 5-ns Read Time, Monolithically Stacked on Si CMOS,” 2025 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 29.4
7. Junmo Lee, et al., “Monolithic 3D Integration of Dual-Gated ALD Oxide-Channel Non-Volatile Capacitive Memory on 40nm Si CMOS for Digital Compute-in-Memory,” 2025 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 28.3
8. Jung-Kyun Kim, et al., “Designing Oxide-Channel FeFETs for 1T Embedded Memory,” 2025 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 29.7