Chip Industry Week In Review


Dealmaking Amkor inked a 10-year agreement with TSMC to provide advanced packaging and test services in Arizona, tying TSMC’s U.S. fab expansion to domestic OSAT capacity. Trump said in a post that Apple will partner with Intel on chip design and production in the U.S., marking a second reported win for the chipmaker this month. Intel Foundry will also reportedly manufacture 3 million... » read more

Research Bits: June 15


NAND in space Researchers from Georgia Institute of Technology and Pennsylvania State University built ferroelectric NAND flash memory chips that can withstand up to 30 times higher radiation levels compared to conventional NAND. “If you send traditional flash memory to space, the radiation interacting with flash memory’s trapped electric charge can easily corrupt the data,” said Asif... » read more

Analyzing Rowhammer Vulnerability in Monolithic 3D IWO eDRAM for Edge (ASU, Georgia Tech)


Researchers from Arizona State University and Georgia Institute of Technology published “Thermal- and Aging-Aware Rowhammer Vulnerability Analysis of Monolithically-Integrated IWO eDRAM for Edge Platforms”. "This work presents the first comprehensive temperature- and aging-aware vulnerability analysis of amorphous Indium Tungsten Oxide (IWO) embedded DRAM (eDRAM), a promising next-... » read more

Oxides Bring Low Leakage Transistors To Leading-Edge Memories


AI workloads need to position more memory that uses less power in ever-closer proximity to computational logic. That overriding imperative is driving new memory designs and new materials exploration across a wide range of applications, including cache memory, working memory, as well as a new category, non-volatile memory used for direct computation. The largest of these, by volume, is workin... » read more

Chip Industry Technical Paper Roundup: Dec 30


New technical papers recently added to Semiconductor Engineering’s library: [table id=509 /] Find more semiconductor research papers here. » read more

Physical Modeling and Benchmarking for 2T-SOT-MRAM (Georgia Tech, MIT, Cornell)


A new technical paper titled "Modeling and Optimization of Two-Terminal Spin-Orbit-Torque MRAM" was published by researchers at Georgia Institute of Technology, MIT, and Cornell University. Abstract "This paper presents physical modeling and benchmarking for two-terminal spin-orbit torque magnetic random-access memory (2T-SOT-MRAM). The results indicate that the common SOT materials that ... » read more

Chip Industry Technical Paper Roundup: Dec. 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=499 /] Find more semiconductor research papers here and in the most recent Chip Industry Week in Review.   » read more

Boosting Memory Bandwidth Availability By Salvaging Idle I/O Bandwidth Resources (Georgia Tech)


A new technical paper titled "Pushing the Memory Bandwidth Wall with CXL-enabled Idle I/O Bandwidth Harvesting" was published by researchers at Georgia Institute of Technology. Abstract "The continual increase of cores on server-grade CPUs raises demands on memory systems, which are constrained by limited off-chip pin and data transfer rate scalability. As a result, high-end processors ty... » read more

Interplay Between the Row Hammer Effect and Floating Body Effect in Monolithic 3D Stackable 1T1C DRAM (Georgia Tech)


A new technical paper titled "Row Hammer Effect and Floating Body Effect of Monolithic 3D Stackable 1T1C DRAM" was published by researchers at Georgia Institute of Technology. Abstract "Monolithic 3D stackable 1T1C DRAM technology is on the rise, with initial prototypes reported by the industry. This work presents a comprehensive reliability study focusing on the intricate interplay between... » read more

Chip Industry Technical Paper Roundup: Nov. 4


New technical papers recently added to Semiconductor Engineering’s library: [table id=488 /] Find more semiconductor research papers here. » read more

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