Hunting For Open Defects In Advanced Packages

No single screening method will show all the possible defects that create opens.


Catching all defects in chip packaging is becoming more difficult, requiring a mix of electrical tests, metrology screening, and various types of inspection. And the more critical the application for these chips, the greater the effort and the cost.

Latent open defects continue to be the bane of test, quality, and reliability engineering. Open defects in packages occur at the chip-to-substrate, and substrate-to-board interfaces and connections within the substrate. These defects typically are created during manufacturing, but they often pass final test. With sufficient thermal cycling in the field, these defects become full opens or shorts.

Unfortunately, there is no easy way to find these defects. Simple electrical tests are insufficient for detecting latent defects within the low-resistance connection path, from chip/substrate bond to the bump/pin at the bottom of the package. And inspection, which is effective for detecting latent defects at the top and bottom connections, cannot find defects within the substrate or redistribution layer (RDL).

Achieving 100% inspection is expensive, too. It requires assembly facility managers to invest in new systems with sufficient throughput and metrology capabilities.

Even then, it’s a matter of knowing what kinds of tests to use when. For substrate latent open defects, an electrical test can be effective if engineers use outlier test detection techniques. With advanced packaging solutions, design-for-test (DFT) circuitry at the signal pins provides engineers with additional test methods, to which data analytic solutions such as outlier detection can be applied.

Latent open defect detection has been a problem for more than a decade, but the challenge is becoming harder. The drive for significantly lower escape rates, normally measured in parts per million, and the advent of advanced packing technology — 2.5D, 3D-IC and SiP — have heightened the industry’s awareness of package defects. This is partly due to the fact that many devices developed with these advanced technologies are expensive, and partly due to a more complex assembly process that provides more opportunities for defects to creep in.

“For many customers, assembly and packaging is somewhat of a black hole,” said Greg Prewitt, director of Exensio solutions at PDF Solutions. “There are many steps that occur during assembly and packaging that can contribute to yield loss, quality issues, and impact long term reliability. Having product lifecycle data that includes assembly and packaging is very important for fully implementing device traceability from the final packaged device, even in the end-market system, all the way back to the source wafer.”

Wirebond is most prevalent packaging technology for semiconductor devices, but it’s not sufficient for the density of power and signal connections needed for phones and high-end computing applications, such as AI and enterprise servers. The connection technologies of choice here are bumps and microbumps.

“Critical parameters to be controlled in bump and pillar processes include bump height, position, diameter, shape, and coplanarity,” said Tim Skunes, vice president of R&D at CyberOptics. “All are critical to ensure reliable connections. Inter-chip connections have proven to be prone to field failures as the effects of thermal stress on disparate materials accumulate over time,”

Field-failures due to package defects have a laundry list of costs, ranging from the actual cost of the known good die to the impact on the supplier’s reputation and, in the case of mission- and safety-critical systems, safety risks to the user and potential financial liability to the device manufacturer. As a result, both test and metrology suppliers anticipate automakers will become even more involved with the assembly and package suppliers within their respective supply chains.

“We are already seeing automakers drive changes to conventional package test and inspection in order to avoid reliability fails,” said Olivier Dupont, product marketing manager in KLA’s ICOS Division. “Screening potential latent package defects can make a big difference to a vehicle’s long-term functionality across a variety of vehicle features, such as entertainment, functional safety, and assisted driving. To limit the defect risks, we have been developing inspection module metrology modules with higher resolution, accuracy, precision and repeatability. We also are getting smarter about linking observed package defects to the long-term reliability of the package.”

Package defects to screen
So what makes package opens so hard to detect? From a high level of abstraction, a package is a bunch of metallic connections between the semiconductor die and the system. Defects can occur within each connection (opens/increase in resistance) or between connections (shorts/high resistance between).

Not all defects cause serious problems. While a a signal path defect can kill a device, a power path defect may never cause an issue. But not all of these are easy to find. Counter-intuitively, low-resistance paths make it a challenge to detect open latent defects. These defects change from a low resistance into a complete open at a latter point in time.

“Anytime we have parallelism in the circuits and defects get masked — meaning they are not easily resolvable to a single net — this proves to be challenging,” said Sam Jonaidi, chief offerings director for automotive at National Instruments. “For instance, power pins/circuits fall in this category, and traditionally have been compensated through redundancy. As an example, if I have 40 ground pins on a package equally distributed around the die periphery, then having a missed connection on one should not adversely impact the operation of device.”

Today, semiconductors can use a wide range of packaging technology. Wirebond packaging accounts for about 75% of semiconductor devices. Next on the pareto chart is ball-grid array, also called C4 bumps, which comes in a variety of flavors. Below that is 2.5D/3D packaging, which today represents only a small percentage of the total market share, although that percentage is growing.

Open defects can occur regardless of the packaging technology used, and they occur in the same three locations. These locations affect how these devices can be screened.

Fig. 1: Conceptual diagram of a package. Source: Semiconductor Engineering/Anne Meixner

Connections can be wires, bumps, microbumps, substrate vias, long interconnects within a silicon interposer, and pins. Any of these can cause defects. In a flip chip, for example, those defects can stem from die bumps, the connection quality between die and substrate, top substrate bumps, interconnect within the RDL, and bottom side substrate bumps.

Fig. 2: Flip-chip BGA package. Source UTAC

The redistribution layers within flip-chip substrates can range from three to seven layers.

Fig. 3: Redistribution layers and electroplating of traditional substrates. Source Brewer Science

Every via in an RDL path creates a point for an open or weak contact. The number of layers in 2.5D and 3D packages also varies. Given the mature silicon technology for the interposer, design engineers and engineering managers are more concerned about micro-bump defects.

“Predictably, as advanced packaging technology has gained traction, the size and pitch of bumps and pillars has decreased, and their number has increased. Bumps for the C4/flip chip process, now a very mature process, are 75µm to 200µm in diameter and similarly pitched,” observed Skunes. “With the introduction of lead-free processes, size decreased somewhat to 75µm to 150µm. Copper pillar processes, currently mainstream, decoupled bump height from diameter and allowed manufacturers to decrease diameters to 50µm to 100µm. Next-generation processes, some of which are coming online now, use micro-pillars with 10µm to 30µm diameters.”

“The most problematic one is probably the microbump connecting the pad to the substrate,” said Nir Sever senior director product marketing at proteanTecs. “This is because it is ‘hidden’ once the die is assembled on the substrate. In most cases, a latent defect can be detected only by sensitive resistance measurement. It is also very difficult to distinguish the source of the failure being at the near-end or the far-end of the interconnect. UCT (Universal Chip Telemetry) provides visibility during test, but also in mission-mode, of lane connectivity with a granular resolution if an issue stems from either pin or the connecting substrate.”

Others agree. “We did some studies with a customer where we measured resistance through various poorly formed solder joints, and it’s really hard to correlate,” said Scott Jewler COO at SXVR. “So it’s difficult to find these with an electrical test.”

Why do latent open defects matter so much? Thermo-cycling of the device in the field produces a mechanical stress that turns a slightly resistive contact into a complete open. Package designs manage this thermo-cycling through careful design.

Still, that assumes a perfectly manufactured device. Manufacturing process controls can increase yield, but random defects or process excursions can result in weak metallurgical connections. These need to be screened at some point in the manufacturing process.

Fig. 4: Package defect Screening Opportunities. Source: Semiconductor Engineering/Anne Meixner

Inspection options for open defects
The perceived inability of electrical test to find latent open defects has been pushing manufacturing facilities to boost inspection.

“Inspection is almost a mandate, since electrical testing does not always catch all defects especially latent failures,” said Jonaidi. “As an example, we can surmise a bad wire bond optically. Yet it will pass final test with flying colors, and fail in the field upon time and temperature.”

Inspection of bumps on die, or substrates prior to assembly, gives engineers the opportunity to detect poorly formed bumps. Multiple wavelengths can be used for inspection, with optical wavelengths being the most prevalent. Yet this can be time consuming, which is why companies such as KLA and CyberOptics have developed inspection equipment that permits higher throughput at equal or better coverage.

“Many customers, especially in higher risk markets like automotive applications, are requiring 100% inspections. Other optical inspection technologies are challenged to provide 100% inspection with enough accuracy and precision at production throughputs, and often use a sampling strategy, extrapolating measurements of a subset of features to characterize the whole population,” said CyberOptics’ Skunes. “Many also require separate passes for 2D and 3D measurements. The MRS sensor’s high speed and ability make both 2D and 3D measurements in a single pass allow it to deliver accurate, repeatable results from a single pass at throughputs in excess of 25 wafers per hour.”

Inspection after assembly requires other equipment, because it’s not possible to inspect everything using optical technology. X-ray inspection is the most common for sub-surface images, but only recently has equipment been able to do this at production speeds.

“In an X-ray systems you have an X-ray source that goes through the device, and you measure the absorption with a detector,” said SVXR’s Jewler. “Our detector’s dynamic range enables a very precise detection of small changes in the thickness of the solder joints.”

Wafer and package test also can damage a bump or pin, thereby prompting some manufacturers to install an inspection step prior to assembly and after final test.

“Package inspection typically occurs two times. First, after the assembly of final packages, before final test, and, a second time, once package testing is completed prior to shipping out the devices,” said KLA’s Dupont. “Inspection of bare dies can also be performed before package assembling. The ICOS F160 inspects bare dies after dicing to check for cracks before sending the dies to subsequent assembly process steps.”

Electrical test options for open defects
Missing from the inspection techniques just discussed is the ability to view defects within the substrate. Electrical test can do this, but the process isn’t straightforward.

At final test product engineers first apply opens and shorts to detect issues with the product and issues with test cell components, such as loadboards.

“Shorts and opens are easy to detect,” said Jonaidi. “Resistive measurements are not as easy since resistive values are so low and hard to measure. We rarely have access for 4-point Kelvin measurements.”

These small resistance changes due to poorly formed solder bumps, solder joints and substrate interconnects do prove challenging for detection with electrical tests. Yet it is not impossible, and it is necessary for defects within a substrate (RDL).

One industry insider recalled an incident involving field returns that indicated a package failure. Analysis engineers narrowed it down to a specific package substrate supplier experiencing periodic excursions rather than an overall process issue and determined that the usual suspects — flip-chip solder ball or the ball-grid array solder ball — were not the cause. The real problem was a weak bond in substrate vias.

As it turned out, Ohm’s Law could detect these defects, but only if engineers applied part average testing instead of spec-based pass/fail limits. The engineers looked to an existing signal output voltage test to screen for these defects, specifically VoutLow. The output driver required about a 20-mA current draw. Thus, every 1 ohm increase in resistance equals 10mV, and the engineers determined they needed to detect a 3 ohm increase.

The current pathway goes from the ATE pin electronics card (PEC) through the load board and package to the signal output driver circuit. This path has multiple sources of variation in the resistance path, which naturally need to be considered in the part average testing determined limits.

After finding similar problems at other substrate suppliers, the engineers refined the part average testing (PAT) approach, shifting from static to dynamic PAT.

This same principle of detecting outliers needs to be applied with advanced packaging. Assessing the connection between chiplets requires the application of DFT-based test methods for parametric tests, such as timing and voltage margining capabilities commonly found in SerDes circuits.

“Advanced packaging (2.5D/3D/SiP/chiplet) has new challenges not addressed before,” said proteanTecs’ Sever. “It is all about moving up from simple pass/fail to parametric measurements — which are required due to increasing frequencies and low-count I/O interfaces like SerDes — to massively parallel I/Os like HBM, OpenHBI, AIB, Glink, and BoW. These massively parallel interfaces, from thousands to tens of thousands of I/Os, require measurement-based data analytics to make sense of the tremendous amount of data from even a single chip.”

Package latent open defects always have been a challenge to detect. Several industry trends—zero parts per million for automotive to hundreds of parts per million in the consumer sector and for advanced packaging in high-end computing — point to the need for a more focused effort to detect them earlier.

The deceptive nature of these defects has prompted engineers to design DFT features into I/O circuitry, to apply outlier-based pass/fail limits to electrical tests, and to deploy 100% inspection after critical process steps. Standard contact tests often miss imperfect solder connections, be they in wire bond or ball grid array package types. In applying optical and X-ray based detection screens engineers can detect defects at the top and bottom with sufficient confidence. But those techniques still cannot detect metallurgical defects in a substrate’s RDL.

Ultimately the detection costs need to be balanced with the risk of a field failure. That will determine the mix of electrical and inspection techniques used to find the elusive latent open defect.

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David Leary says:

Thanks for an interesting article Anne. I would add that prevention of manufacturing process excursions that result in outlier material and associated yield loss and latent defects, should be a focus area ahead of relying on testing and inspection. For example, analysis of variance (ANOVA) applied to a substrate manufacturer’s KPI metrology and in-line acceptance testing pays great dividends in quality assurance and CPI. One other comment… it’s my experience that electrical O/S test for defects is significantly improved when performed hot (eg > 80C).

Krasi Popov says:

You should focus on hot/cold stress test to be eliminate such a problems in advance, and to do this PE groups must implement PAT technics in wafer level.

Anne Meixner says:

Krasi, Hot/Cold test at package level can be done. Typically, at package level, they remove one of the temp sockets.

PAT can be used at wafer and package. I recently wrote an article on this.

Yet the defects to be tested for in this article are related to package defects, and PAT at Wafer level won’t help. PAT at package level does as the description of one engineering team solved the RDL via crack.

Anne Meixner says:

So glad you found this article of interest.
You are quite right to point out that testing units at hot will make it easier to find resistive opens.
yet when you are only looking for a 3 ohm difference, it might be hard.

Your point about substrate manufacturers using statistical process control monitors, CPK, KPIs to reduce excursions as described in this article would make good use.

Jesse says:

Great article. I am curious if there has been any progress in electrical testing to screen latent open defects since this article was written.

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