Planning Ahead For In-System Test Of Automotive ICs


Automobiles are increasingly more like electronic devices than mechanical platforms. As a share of the total cost of a car, electronics components have grown from about 5% in 1970 to 35% in 2010. Electronics are projected to account for 50% by 2030 (Deloitte, 2019). Some of the electronics are for passive operations, like display or In-Vehicle Infotainment (IVI) systems, but a growing proportio... » read more

AI Chips Driving Need For New Test Implementation Methodologies


Artificial intelligence has never been more in the news than it is today.  From picking stock market investments to autonomous driving, we have heard about what AI can do when it works and what happens when it goes awry. The consequences are huge if AI doesn’t work which puts a lot of pressure on hardware engineers to ensure that their chips can be extensively tested for proper and safe func... » read more

Squeezing Out More Test Compression


The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been quite effective at containing test costs. For many designs, standard test compressions is enough, but ICs for use in automotive and medical devices require a higher manufacturing test quality, which t... » read more

Verification Pilgrims Show A Historical Case For DFT


The Mayflower Steps, where the Pilgrims are believed to have embarked on their journey to America, are located in the beautiful Barbican area of Plymouth, a small town in the southwest of England. As the lone American working for Moortec, a British company based in Plymouth, I stood and stared at them this past September. Separated by a few yards of distance but 399 years of history I found my... » read more

A Breakthrough In Silicon Bring-Up


The current semiconductor market is seeing increasingly complex silicon devices for applications like 5G wireless communications, autonomous driving, and artificial intelligence. One of the ways designers are working to control design time and cost is through the adoption of IJTAG (IEEE 1687) for a plug-and-play style IP integration during design. The benefits of using IJTAG are still emerging,... » read more

Simplifying Silicon Bring-Up And Debug On ATE equipment With ATE-Connect


The silicon bring-up process is ripe for improvement. Tessent SiliconInsight with ATE-Connect technology eliminates communication barriers between proprietary tester-specific software and DFT platforms, which accelerates debug of IJTAG devices, speeds product ramps, and reduces time-to-market for products in 5G wireless communications, autonomous driving, and artificial intelligence. Read mo... » read more

The Single Best DFT Move You Can Make


A proven method to simplify a complex problem is to break it into smaller chunks. In the case of today’s large, complex SoCs, this means using hierarchical methods to design the blocks, then combine the results at the top level. While this sounds obvious, it hasn’t always been practical or technologically feasible to perform some tasks, like DFT, at the block level and translate that work s... » read more

Hierarchical DFT: Proven Divide-And-Conquer Solution Accelerates DFT Implementation And Reduces Test Costs


Implementation of the most challenging DFT tasks is greatly simplified by the proven and widely-adopted automation available in Tessent products. This whitepaper describes the basic components of an RTL-based hierarchical DFT methodology, the benefits that it provides, and the tool automation that is available through Mentor’s Tessent products. The focus is on the techniques and automation of... » read more

The Great Test Blur


As chip design and manufacturing shift left and right, concerns over reliability are suddenly front and center. But figuring out what exactly what causes a chip to malfunction, or at least not meet specs for performance and power, is getting much more difficult. There are several converging trends here, each of which plays an integral role in improving reliability. But how significant a role... » read more

Hierarchical DFT On A Flat Layout Design


The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules.  Hierarchical DFT divides the design into smaller pieces, creates test structures and patterns at the core level, then retargets the core patterns to the chip level. But, if you need to perform the physical place and route on the full flat design, can you still take a... » read more

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