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Author's Latest Posts


Reconfigurable eFPGA For Aerospace Applications


Market research reports indicate about 10% of all dollar revenue of FPGA chips is for use in aerospace applications, and DARPA/DoD reports indicate about one-third of all dollar volume of ICs purchased by U.S. aerospace are FPGAs. FPGAs clearly are very important for aerospace applications because of a combination of short development time and the long mission life of many aerospace applica... » read more

Flexible, Energy-Efficient Neural Network Processing At 16nm


At Hot Chips 30, held in August in Silicon Valley, Harvard University (Paul Whatmough, SK Lee, S Xi, U Gupta, L Pentecost, M Donato, HC Hseuh, Professor Brooks and Professor Gu) made a presentation on “SMIV: A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IOT Devices. ” (Their complete presentation is available now on the Hot Chips website for attendees and will be p... » read more

Sandia Labs’ New Configurable SoC


At DAC 2018, held in June in San Francisco, Sandia Labs made a public presentation for the first time describing its first SoC using eFPGA, called Dragonfly. This is the first public disclosure by any organization describing its requirements, architecture and use cases for the new technology option of embedded FPGA. John Teifel led the project for Sandia National Laboratories. Sandia has ... » read more

Reconfigurable AI Building Blocks For SoCs And MCUs


FPGA chips are in use in many AI applications today, including Cloud datacenters. Embedded FPGA (eFPGA) is now becoming used for AI applications as well. Our first public customer doing AI with EFLX eFPGA is Harvard University, who will present a paper at Hot Chips August 20th on Edge AI processing using EFLX: "A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IoT Devi... » read more

Architects: How To Get The Most Out Of eFPGA


At Flex Logix, we are working with customers with a wide range of applications: MCU, IoT, SoC, Networking, Wireless Base Station, Communications, Data Center, AI, Vision, Signal Processing and Aerospace. Their needs and their situations are all very different, but we have noticed some common learnings across the range of applications as people learn how to use eFPGA. 1. Use as little eFPGA a... » read more

Timing Signoff Methodology For eFPGA


An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the int... » read more

Introduction To eFPGA Software


In February, we covered “Introduction to eFPGA Hardware.” Now in April, we’ll provide an introduction to eFPGA software. An eFPGA is a block of programmable logic from a few thousand to a few hundred thousand LUTs (look up tables) of programmable logic that is embedded in an SoC. The clock(s) for the eFPGA come from the SoC. The configuration of the eFPGA is done by the SoC... » read more

eFPGA: Think Differently & Experiment


New technologies are never overnight successes and usually develop in new applications. Arm and other embedded processors today are a huge success and pervasive in almost all chips. It took Arm more than five years to win the first five customers. The first applications were not competitive with Intel’s PC dominance but instead filled needs in emerging applications such as mobile phones an... » read more

Introduction To eFPGA Hardware


Intel builds processor chips and Arm provides processor cores to integrate into chips. Xilinx and Intel (nee Altera) build FPGAs and a range of new startups provide embedded FPGA (eFPGA) to integrate into chips: Achronix, Flex Logix, Menta and QuickLogic. As the diagram above shows, an FPGA chip is a core (the “fabric”) which is surrounded by various kinds of I/O including SERDES,... » read more

The Importance Of Metal Stack Compatibility For Semi IP


Architects and front end designers usually leave the back end to the physical designers: they know there can be different numbers of metal layers, but may not realize the characteristics of each metal layer may vary layer by layer as well and that different chips use different metal stack ups to optimize for their requirements. This slide from IDF14 shows a simple summary of the breadth of v... » read more

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