Week In Review: Manufacturing, Test


The coronavirus (COVID-19) continues to have an impact on most, if not all, industries. This includes the electronics, semiconductor and related segments. International Data Corp. (IDC) has released a report on the company’s view on the impact the COVID-19 virus will have on the semiconductor market. The report provides a framework to evaluate the market impact through four scenarios. "... » read more

Week In Review: Auto, Security, Pervasive Computing


AI, machine learning Cadence says it has optimized its Tensilica HiFi digital signal processor IP to efficiently execute TensorFlow Lite for Microcontrollers, which are used in Google’s machine learning platform for edge. This means developers of AI/ML on the edge systems can now put better audio processing on edge devices with ML applications like keyword detection, audio scene detection, n... » read more

Aging Analysis Standard Solidifies Through Collaborative Effort


By Ahmed Ramadan, Greg Curtis, Harrison Lee, Jongwook Kye, and Sorin Dobre We live in a connected world and it is estimated that by 20251 the total amount of worldwide data will swell to 163 ZB, or 163 trillion gigabytes. This rapid growth in data expansion is driving an explosion in new designs and new requirements for consumer, data center, automotive, and Internet of Things (IoT) applicat... » read more

Week In Review: Auto, Security, Pervasive Computing


AI The European Union put out a white paper about artificial intelligence. The United States Chief Technology Officer Michael Kratsios criticized the EU stance on Thursday as clumsy. "We found, what they actually put out yesterday, really, I think, in some ways clumsily attempts to bucket AI-powered technologies as either ‘high-risk’ or ‘not high-risk,’” he said, according to a news ... » read more

5/3nm Wars Begin


Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond. The decision involves the move to extend today’s finFETs to 3nm, or to implement a new technology called gate-all-around FETs (GAA FETs) at 3nm or 2nm. An evolutionary step f... » read more

CES 2020 Highlights New Automotive Tech


Another year, another Consumer Electronics Show (CES) packed with innovative technology. In the many years I’ve been coming to the show, I’ve seen it evolve from a launchpad for the year’s mainstream devices – televisions, laptops, smartphones – to encompass all manner of smart devices within the home and beyond. As the head of automotive at Arm, it’s that ‘beyond’... » read more

The Growing Challenges Of 5G Reliability


The test field is getting more complicated as chips become larger, more heterogeneous, and subject to almost constant changes. Nowhere is this more evident than in 5G, where standards are still evolving and use cases are still being defined. Without passing test, no technology advances. But those definitions are subject to change, and they can change again over time. The communications in... » read more

Week In Review: Manufacturing, Test


Chipmakers United Microelectronics Corp. (UMC) has announced the readiness of its new 22nm process. The process enables new 22nm designs or allows customers to migrate from 28nm to 22nm. UMC’s 22nm maintains its existing 28nm design architectures. UMC's 22nm process features a 10% area reduction, better power-to-performance ratio and enhanced RF capabilities, compared to the company’s 2... » read more

Week In Review: IoT, Security, Auto


Internet of Things SiFive is bringing RISC-V to IoT makers and university developers through the RISC-V-based SiFive Learn Initiative, an open-source learning package that can be used to create a low-cost RISC-V hardware compatible with AWS IoT Core. The development platform SiFive Learn Inventor has a software package and education enablement course. It includes: The programmable SiFive Lear... » read more

Planning For Panel-Level Fan-out


Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

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