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Chiplets: A Solution For The Shortage Of Chips


These days, there are new reports on the shortage of chips almost every day. Currently, this issue is affecting mainly car manufacturers such as Audi, Ford, and more. But other system manufacturers, such as in the machine construction industry, are also facing this challenge. Even manufacturers of mass-produced articles such as game consoles are reporting the same problems. The problem is sure ... » read more

Debug And Traceability Of MCMs And Chiplets In The Manufacturing Test Process


Single die packages and products have been the norm for decades. Moreover, so has multi-chip modules (MCMs) or system in package (SiP) for quite some time. Understandably, with ASICs and SoCs becoming larger while silicon geometries continue to get smaller, there is an opportunity to combine even more functionality into a smaller form factor for the end product. Hence, new advancements in desig... » read more

Making Chip Packaging More Reliable


Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

Advanced Packaging For Improved Network Communications


The global demand for data increases day-by-day. At the same time, the data transmission rate will increase to exceed 1 Terabits per second (Tbps) near the middle of this decade. To address this situation and provide a third alternative, engineers are increasingly looking into the chiplet approach with multiple smaller dies integrated in a single package. Only the logic portion that needs to... » read more

EDA, IP Revenues Soar


EDA and IP revenues increased 15.4% to $3.032 billion in Q4 2020, according to a just-released report, with huge increases reported in China and India, and a solid double-digit increase in the Americas. EDA/IP revenue from China increased 66.4% in Q4 EDA/IP compared with the same period in 2019, and for the 2020 calendar year it was up 52.3%. India's spending was up 32% for the quarter. And ... » read more

Many Chiplet Challenges Ahead


Over the past couple of months, Semiconductor Engineering has looked into several aspects of 2.5D and 3D system design, the emerging standards and steps that the industry is taking to make this more broadly adopted. This final article focuses on the potential problems and what remains to be addressed before the technology becomes sustainable to the mass market. Advanced packaging is seen as ... » read more

More Data Drives Focus On IC Energy Efficiency


Computing workloads are becoming increasingly interdependent, raising the complexity level for chip architects as they work out exactly where that computing should be done and how to optimize it for shrinking energy margins. At a fundamental level, there is now more data to compute and more urgency in getting results. This situation has forced a rethinking of how much data should be moved, w... » read more

How Heterogeneous ICs Are Reshaping Design Teams


Experts at the Table: Semiconductor Engineering sat down to discuss the complex interactions developing between different engineering groups as designs become more heterogeneous, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Mai... » read more

Waiting For Chiplet Standards


The need and desire for chiplets is increasing, but for most companies that shift will happen slowly until proven standards are in place. Interoperability and compatibility depend on many layers and segments of the supply chain coming to agreement. Unfortunately, fragmented industry requirements may lead to a plethora of solutions. Standards always have enabled increasing specialization. ... » read more

Hunting For Open Defects In Advanced Packages


Catching all defects in chip packaging is becoming more difficult, requiring a mix of electrical tests, metrology screening, and various types of inspection. And the more critical the application for these chips, the greater the effort and the cost. Latent open defects continue to be the bane of test, quality, and reliability engineering. Open defects in packages occur at the chip-to-substra... » read more

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