Author's Latest Posts


Bonding Issues For Multi-Chip Packages


The rising cost and complexity of developing chips at the most advanced nodes is forcing many chipmakers to begin breaking up that chip into multiple parts, not all of which require leading edge nodes. The challenge is how to put those disaggregated pieces back together. When a complex system is integrated monolithically — on a single piece of silicon — the final product is a compromise ... » read more

Neural Networks Without Matrix Math


The challenge of speeding up AI systems typically means adding more processing elements and pruning the algorithms, but those approaches aren't the only path forward. Almost all commercial machine learning applications depend on artificial neural networks, which are trained using large datasets with a back-propagation algorithm. The network first analyzes a training example, typically assign... » read more

Zeroing In On Biological Computing


Artificial spiking neural networks need to replicate both excitatory and inhibitory biological neurons in order to emulate the neural activation patterns seen in biological brains. Doing this with CMOS-based designs is challenging because of the large circuit footprint required. However, researchers at HP Labs observed that one biologically plausible model, the Hodgkins-Huxley model, is math... » read more

Spiking Neural Networks Place Data In Time


Artificial neural networks have found a variety of commercial applications, from facial recognition to recommendation engines. Compute-in-memory accelerators seek to improve the computational efficiency of these networks by helping to overcome the von Neumann bottleneck. But the success of artificial neural networks also highlights their inadequacies. They replicate only a small subset of th... » read more

Challenges For Compute-In-Memory Accelerators


A compute-in-memory (CIM) accelerator does not simply replace conventional logic. It's a lot more complicated than that. Regardless of the memory technology, the accelerator redefines the latency and energy consumption characteristics of the system as a whole. When the accelerator is built from noisy, low-precision computational elements, the situation becomes even more complex. Tzu-Hsian... » read more

Compute-In Memory Accelerators Up-End Network Design Tradeoffs


An explosion in the amount of data, coupled with the negative impact on performance and power for moving that data, is rekindling interest around in-memory processing as an alternative to moving data back and forth between the memory and the processor. Compute-in-memory (CIM) arrays based on either conventional memory elements like DRAM and NAND flash, as well as emerging non-volatile memori... » read more

Scaling Up Compute-In-Memory Accelerators


Researchers are zeroing in on new architectures to boost performance by limiting the movement of data in a device, but this is proving to be much harder than it appears. The argument for memory-based computation is familiar by now. Many important computational workloads involve repetitive operations on large datasets. Moving data from memory to the processing unit and back — the so-called ... » read more

Moving To GAA FETs


How do you measure the size of a transistor? Is it the gate length, or the distance between the source and drain contacts? For planar transistors, the two values are approximately the same. The gate, plus a dielectric spacer, fits between the source and drain contacts. The contact pitch, limited by the smallest features that the lithography process can print, determines how many transistors ... » read more

New Packaging Roadmap


Historically, the electronics industry has drawn sharp distinctions between the integrated circuit chip, the package that protects it from the environment, and the board that connects it to other devices in a complete system. The circuit and systems worlds have been largely isolated from each other, using different tools, different processes, and different metrics for success. While integrated ... » read more

New Trends In Wafer Bonding


Unable to scale horizontally, due to a combination of lithography delays and power constraints, manufacturers are stacking devices vertically. This has become essential as the proliferation of mobile devices drives demand for smaller circuit footprints, but the transition isn't always straightforward. Three-dimensional integration schemes take many forms, depending on the required interconne... » read more

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