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Katherine Derbyshire

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Katherine Derbyshire is a technical editor at Semiconductor Engineering.

Author's Latest Posts

Preparing For Ferroelectric Devices
By Katherine Derbyshire - 02 Oct, 2024 - Comments: 0

The discovery of ferroelectricity in materials that are compatible with integrated circuit manufacturing has sparked a wave of interest in ferroelectric devices. Ferroelectrics are materials with a permanent polarization, the direction of which can be switched by an applied field. This polarization can be used to raise or lower the threshold voltage of a transistor, as in FeFETs, or it can c... » read more

Reasons To Know IGZO
By Katherine Derbyshire - 15 Aug, 2024 - Comments: 0

Interest in monolithic 3D integration is driven by both compute-in-memory applications and a more general need for increased circuit density. Compute-in-memory architectures seek to reduce the power requirements of machine learning workloads, which are dominated by the movement of data between memory and logic components. Even in conventional architectures, though, placing high-density, high-ba... » read more

New Interconnect Metals Need New Dielectrics
By Katherine Derbyshire - 23 Jul, 2024 - Comments: 0

Just as circuit metallization must evolve to manage resistance as features shrink, so must the dielectric half of the interconnect stack. For quite some time, manufacturers have needed a dielectric constant (k) less than 4, which is the value for SiO2, but they have struggled to find materials that combine a low dielectric constant with mechanical and chemical stability. In work presented at... » read more

Ruthenium Interconnects On Tap
By Katherine Derbyshire - 20 Jun, 2024 - Comments: 0

Chipmakers' focus on new interconnect technology is ramping up as copper's effectiveness continues to diminish, setting the stage for a significant shift that could improve performance and reduce heat at future nodes and in advanced packages. The introduction of copper interconnects in 1997 upended the then-standard tungsten via/aluminum line metallization scheme. Dual damascene integration ... » read more

Sidestepping Lithography In Chip Manufacturing
By Katherine Derbyshire - 23 May, 2024 - Comments: 0

Rising lithography costs, shrinking feature sizes, and the need for an alternative to copper are collectively spurring new interest in area-selective deposition. An extension of atomic layer deposition, ASD seeks to build circuit features from the bottom up, without relying on lithography. Lithography will remain a critical tool for the foreseeable future. But it has long been the most expen... » read more

Enabling Advanced Devices With Atomic Layer Processes
By Katherine Derbyshire - 18 Apr, 2024 - Comments: 2

Atomic layer deposition (ALD) used to be considered too slow to be of practical use in semiconductor manufacturing, but it has emerged as a critical tool for both transistor and interconnect fabrication at the most advanced nodes. ALD can be speeded up somewhat, but the real shift is the rising value of precise composition and thickness control at the most advanced nodes, which makes the ext... » read more

Powering CFETs From The Backside
By Katherine Derbyshire - 21 Mar, 2024 - Comments: 0

The first CMOS circuits to incorporate backside power connections are likely to be based on stacked nanosheet transistors, but further down the road, planners envision complementary transistors (CFETs) that vertically integrate stacked NFET and PFET devices. With at least twice the thickness of a nanosheet transistor, connecting CFETs to each other and to the rest of the circuit is likely to... » read more

Building CFETs With Monolithic And Sequential 3D
By Katherine Derbyshire - 22 Feb, 2024 - Comments: 0

Successive versions of vertical transistors are emerging as the likely successor to finFETs, combining lower leakage with significant area reduction. A stacked nanosheet transistor, introduced at N3, uses multiple channel layers to maintain the overall channel length and necessary drive current while continuing to reduce the standard cell footprint. The follow-on technology, the CFET, pushes... » read more

3D Integration Supports CIM Versatility And Accuracy
By Katherine Derbyshire - 18 Jan, 2024 - Comments: 0

Compute-in-memory (CIM) is gaining attention due to its efficiency in limiting the movement of massive volumes of data, but it's not perfect. CIM modules can help reduce the cost of computation for AI workloads, and they can learn from the highly efficient approaches taken by biological brains. When it comes to versatility, scalability, and accuracy, however, significant tradeoffs are requir... » read more

Modeling Compute In Memory With Biological Efficiency
By Katherine Derbyshire - 19 Dec, 2023 - Comments: 0

The growing popularity of generative AI, which uses natural language to help users make sense of unstructured data, is forcing sweeping changes in how compute resources are designed and deployed. In a panel discussion on artificial intelligence at last week’s IEEE Electron Device Meeting, IBM’s Nicole Saulnier described it as a major breakthrough that should allow AI tools to assist huma... » read more

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