Powering CFETs From The Backside

The first CMOS circuits to incorporate backside power connections are likely to be based on stacked nanosheet transistors, but further down the road, planners envision complementary transistors (CFETs) that vertically integrate stacked NFET and PFET devices.

With at least twice the thickness of a nanosheet transistor, connecting CFETs to each other and to the rest of the circuit is likely to challenge any interconnect scheme, whether it uses the backside, the frontside, or both.

Backside power (see related article) is attractive because backside power lines can be both fatter and shorter, reducing resistance and IR drop. Moving power lines to the backside also simplifies signal routing in the first few metal layers, potentially allowing designers to relax the metal pitch in those layers. Ben Sell, vice president of technology development at Intel, explained that if using a more relaxed pitch eliminates an EUV exposure or reduces the need for EUV multi-patterning techniques, that savings alone will justify the cost of backside power implementation.

Backside power does not affect the transistor dimensions, and it may not make the cell smaller. There still needs to be room for the backside connection. However, in a short course at the 2022 IEEE Electron Device Meeting, Imec’s Gaspard Hiblot argued that backside power rails can support scaling from six to five tracks in a standard cell while keeping channel length the same.[1]

CFETs, however, do make the standard cell smaller. Moving the PFET and NFET devices into a single vertical stack potentially recovers almost half the transistor footprint while keeping channel length the same.

Mauro Kobrinsky, an Intel fellow, said backside power is the most area-efficient connectivity solution for CFETs. Routing exclusively through the frontside requires a high aspect ratio etch to reach the bottom device and imposes severe routing congestion. In results presented at December’s IEDM conference, Intel demonstrated a backside power implementation that runs “PowerVia” connections from the side of a nanosheet transistor down to a buried power grid. Relative to the buried power rail approach, which runs vias up to M-0 and then back down through the substrate, the PowerVia approach reduces cell height to five tracks.

Fig. 1: Three interconnect topology options for CFETs use all frontside connections (a), frontside connections for top device and backside connections for bottom device (b), and PowerVia to connections between stacked devices as well as front and back interconnect stacks. Source: Intel/IEDM [2]

Wafer distortion challenges bottom contacts
According to Kobrinsky, the emergence of CFETs will require further evolution, with a bottom contact direct to the bottom device. This scheme envisions using a structure comparable to a PowerVia between the top device and the buried power grid. Because CFETs gain a lot of area by stacking the transistors, there is space available for relatively large vias. While this is non-trivial, the progression from nanosheet transistors with buried power rails, to CFETs with bottom contacts, is incremental rather than revolutionary.

The biggest process challenges for backside power are the high aspect ratio etch and fill to get to the bottom of the device, extreme silicon thinning to allow access to the devices from the bottom, and bonding-related distortion for the backside lithography. Backside contacts, in particular, will require very challenging alignment to the devices being contacted, probably within 10nm or better, so bonding-related distortion is a serious concern.

EV Group director of business development Thomas Uhrmann explained that bonding-related distortion occurs when the device wafer, with complete frontside metallization and passivation, is fusion bonded to a bare silicon “carrier” wafer. The bonding process essentially stretches the device wafer, forcing it to conform to the carrier wafer. Removal of all but about 500nm of the original silicon thickness — necessary to allow access to the device layer — relaxes some of the resulting stress and allows the device layer to conform itself to the new support.

However, the final topography of the device layer depends on the exact circuit structure, and is therefore difficult to predict in advance. Achieving the overlay precision required for backside contacts requires careful measurements of the wafer shape and field-by-field lithography corrections. Naoto Horiguchi, logic and CMOS program director at imec, said the process is very time consuming in research settings. For mass production, he believes the industry will need to reduce the amount of distortion and find a more efficient way to compensate for it.

Managing the middle dielectric
Making contact from the top device in a CFET to the bottom power grid requires a high aspect ratio etch. Intel views this process as an extension of its PowerVia scheme, not a radical change. Relative to nanosheet transistors, though, CFETs need a middle dielectric layer to isolate the NFET and PFET from each other. Depending on the integration scheme, this layer can be created at the beginning, as a dielectric layer within the Si/SiGe heterostructure that ultimately will form the nanosheet structure. Alternatively, the selective etching and oxidation step that creates and isolates the channel nanosheets also can create a thicker oxide for the middle dielectric layer. If the middle dielectric is part of the hetero-structure from the beginning, then the deep etch process for the top device contact will need to account for the dielectric layer. If the dielectric is inserted later, it will require careful control of Si/SiGe etch selectivity.

Sequential 3D integration proposes a more challenging and ambitious approach to CFETs, requiring more process changes. It blurs the line between the wafer process and the packaging process, as wafers within a sequential 3D stack can potentially have different kinds of active elements, or could contain wiring and passive components exclusively. At least in principle, it would be possible to run power and signals for the bottom devices to the backside of the bottom wafer, and power and signals for the top devices to the top side of the top wafer, Horiguchi said. In practice, though, close coupling and a gate-to-gate connection between the NFET and PFET transistors is essential to a CFET cell.

Marko Radosavljevic, Intel principal engineer, observed that the thickness of the middle dielectric separating the two transistors is constrained by other aspects of the circuit design, like capacitance and power dissipation. A sequential 3D process might appear to simplify manufacturing, but the relatively thick middle dielectric layer it would produce might fail to meet other constraints.

Getting rid of heat
Once CFETs are constructed, either monolithically or sequentially, the next big concern is heat dissipation. At the chip level, backside power helps heat dissipation. The fatter power lines are less resistive and provide a thermal path to the back of the device. At any specific location, however, the amount of heating still depends on the workload and the local environment. The dielectric layer separating the device from the backside is a barrier to heat transfer. Even if overall heat extraction is sufficient, hotspots might appear without the heat spreading effect of the bulk silicon substrate. In work presented at December’s IEEE Electron Device meeting, Anabela Veloso and colleagues at Imec, noted that replacing the SiO₂ barrier oxide with SiN might improve heat spreading and reduce the risk of hotspots.[3]

Managing heat dissipation from CFETs is still a work in progress. Adding more nanosheets reduces the current density in each individual layer, thereby reducing heating, but also increasing capacitance. Fragmentation of the channel into parallel nanosheets degrades heat dissipation, as the dielectric layers in between are a barrier to heat transport. Even though increasing the number of sheets reduces current density, work presented at the 2022 VLSI Technology Symposium showed that aggressive scaling carries a significant thermal cost. In simulations, a 3-sheet CFET at the N2 node had nearly double the device-level self-heating of an N5 finFET.[4] On the positive side, some of the area recovered by stacking the transistors can be used to make the CFET channels wider, again reducing current density and heating.

The final consideration is circuit noise. In circuits with frontside power lines, Kobrinsky said the power lines help to isolate signal lines from each other, reducing crosstalk. Intel’s PowerVia architecture incorporates noise shields into the front side in lieu of this isolating effect.

Ultimately, though, both the signal and power lines will ultimately need to make their way to the back side and out to the rest of the circuit. As circuit density increases, crowding may become an issue.

Conclusion
Beyond the transistor integration scheme, both backside power and 3D circuit structures expand the design tool box. A backside power grid might incorporate ESD protection or power conditioning elements. As previously discussed, sequential 3D integration can be used to add compute-in-memory elements both above and below the transistor layer. A heterogeneous CMOS platform incorporated into heterogeneous packaging schemes could be the next step in the industry’s quest for more compact, more capable systems.

References

1. Geert Hellings, Gaspard Hiblot, and Julien Ryckaert, “Process Architectures Changes To Improve Power Delivery,” IEDM Short Course 1, San Francisco, Dec. 2022.
2. M. Kobrinsky, et al., “Process Innovations for Future Technology Nodes with Back-Side Power Delivery and 3D Device Stacking,” IEDM, San Francisco, 2023. DOI:10.1109/IEDM45741.2023.10413882
3. Anabel Veloso et al., “Backside Power Delivery: Game Changer and Key Enabler of Advanced Logic Scaling and New STCO Opportunities,” IEDM, San Francisco, Dec. 2023. DOI: 10.1109/IEDM45741.2023.10413867
4. B. Vermeersch, et al., “Self-Heating in iN8–iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters,” 2022 IEEE Symposium on VLSI Technology and Circuits. DOI: 10.1109/VLSITechnologyandCir46769.2022.9830228.

Related Reading
Building CFETs With Monolithic And Sequential 3D
Area benefits are significant for future transistor shrinks, but manufacturing challenges remain.
Will CFETs Help The Industry Go Vertical?
Stacking of nMOS on top of pMOS devices is possible using monolithic or sequential flows. Each has its pros and cons.
Backside Power Delivery Adds New Thermal Concerns
Lack of shielding, routing issues, and new mechanical stresses could have broad impact on standard cell design.