tag: dielectrics

When Cleaning Chips Isn’t Clean Enough
By Gregory Haley - 19 Feb, 2026 - Comments: 0

Key Takeaways Contamination is becoming much more difficult to identify at the most advanced nodes, forcing fabs to rethink how control is achieved. Issues may show up as electrical or statistical anomalies, not particles, and not at time zero. Reliable classification is needed to identify critical contamination and reduce time and effort spent on nuisance failures. For much... » read more

Less Power and Higher Performance With A Nanolaser With Extreme Dielectric Confinement (DTU)
By Technical Paper Link - 16 Feb, 2026 - Comments: 0

A new technical paper titled "A nanolaser with extreme dielectric confinement" was published by researchers at Technical University of Denmark (DTU). Abstract "The interaction between light and matter can be enhanced by spatially concentrating the light field and extending photon dwell time. Plasmonic structures can provide strong light confinement but suffer from ohmic losses. Recent adv... » read more

Impact Of The Film Transfer And Grain Size On The Cu-barrier Properties Of 2D WS2 Films (NUS et al.)
By Technical Paper Link - 29 Jan, 2026 - Comments: 0

A new technical paper titled "Enhancing Cu-barrier properties of 2D-WS2 barriers: The role of grain size and surface passivation" was published by researchers at National University of Singapore, AIXTRON, IMiF and Applied Materials. Abstract "Two-dimensional (2D) films, such as tungsten disulfide (WS2), are being considered by the microelectronics industry as promising barrier and liner s... » read more

Channel-Last GAA NS Oxide FET (Stanford, TSMC, ETH Zurich et al.)
By Technical Paper Link - 03 Jan, 2026 - Comments: 0

A new technical paper titled "Channel-last gate-all-around nanosheet oxide semiconductor transistors" was published by researchers at Stanford University, TSMC, ETH Zurich, SLAC National Accelerator Laboratory, and Polish Academy of Sciences. Abstract "As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the t... » read more

Reliability Risks Shift To The Materials Stack
By Gregory Haley - 18 Dec, 2025 - Comments: 0

The semiconductor industry’s push into 3D integration and large-format substrates has fundamentally changed the role of materials in packaging. What were once structural supports and electrical insulators have become critical performance limiters. Modern packages contain far more polymers, adhesives, advanced dielectrics, thermal materials, and composite laminates than previous generations... » read more

Precision Under Pressure: Managing Materials Complexity In Advanced Packaging
By Gregory Haley - 18 Sep, 2025 - Comments: 0

In the race to extend Moore's Law through advanced packaging, the limits of precision are no longer defined solely by lithography. Increasingly, they are dictated by the unpredictable behavior of materials. Semiconductor packaging today is no longer limited to just silicon and copper. It includes an expanding range of polymers, adhesives, dielectrics, exotic metals, along with substrates suc... » read more

Using Glass As A Dielectric In Electronic Packaging
By Dick Otte - 20 Mar, 2025 - Comments: 0

As demand for higher-performance, more compact and energy-efficient electronics continues to escalate, traditional organic based substrates are approaching practical limitations, leading to industry experimentation with alternative materials. To this end, glass substrates have emerged as a promising alternative with distinct benefits for semiconductor packaging. Major chipmakers, including ... » read more

Method To Determine The Permittivity of Dielectric Materials in 3D Integrated Structures At Broadband RF Frequencies
By Technical Paper Link - 25 Sep, 2024 - Comments: 0

A new technical paper titled "Characterizing the Broadband RF Permittivity of 3D-Integrated Layers in a Glass Wafer Stack from 100 MHz to 30 GHz" was published by researchers at NIST. Abstract "We present a method for accurately determining the permittivity of dielectric materials in 3D integrated structures at broadband RF frequencies. With applications of microwave and millimeter-wave ele... » read more

Research Bits: Aug. 20
By Jesse Allen - 20 Aug, 2024 - Comments: 0

EUV mirror interference lithography Researchers from the Paul Scherrer Institute developed an EUV lithography technique that can produce conductive tracks with a separation of just five nanometers by exposing the sample indirectly rather than directly. Called EUV mirror interference lithography (MIL), the technique uses two mutually coherent beams that are reflected onto the wafer by two id... » read more

New Interconnect Metals Need New Dielectrics
By Katherine Derbyshire - 23 Jul, 2024 - Comments: 0

Just as circuit metallization must evolve to manage resistance as features shrink, so must the dielectric half of the interconnect stack. For quite some time, manufacturers have needed a dielectric constant (k) less than 4, which is the value for SiO2, but they have struggled to find materials that combine a low dielectric constant with mechanical and chemical stability. In work presented at... » read more

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