The Seven Pillars Of IC Package Physical Design


Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs. Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel) The evolving landscape of packagin... » read more

Blog Review: Feb. 14


Siemens’ Dilan Heredia and Karen Chow explain why fast, accurate parasitic extraction (PEX) is essential to design success, especially for the 3 nm node and GAAFETs. Synopsys’ Srinivas Velivala debunks the myth that layout-versus-schematic (LVS) checking is a static step in the chip development process, and details its evolving role in modern SoCs. Cadence’s Mark Seymour digs into a... » read more

Chip Industry Week In Review


By Jesse Allen, Linda Christensen, and Liz Allan.  The Biden administration plans to invest more than $5B  for semiconductor R&D and workforce support, including in the National Semiconductor Technology Center (NSTC), as part of the rollout of the CHIPS Act. Today's announcement included at least hundreds of millions for the NSTC workforce efforts, including creating a Workforce Cente... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan. Cadence introduced an AI-based thermal stress and analysis platform aimed at 2.5D and 3D-ICs, and cooling for PCBs and electronic assemblies. The company also debuted a HW/SW accelerated digital twin solution for multi-physics system design and analysis, combining GPU-resident computational fluid dynamics (CFD) solvers with dedicated GPU hardwar... » read more

Dealing With Noise In Image Sensors


The expanding use and importance of image sensors in safety-critical applications such as automotive and medical devices has transformed noise from an annoyance into a life-threatening problem that requires a real-time solution. In consumer cameras, noise typically results in grainy images, often associated with poor lighting, the speed at which an image is captured, or a faulty sensor. Typi... » read more

Blog Review: Jan. 31


Synopsys' William Ruby argues for a comprehensive energy-efficient design methodology for automotive ICs as today's vehicles demand ever more computing power to support electrification, communication, and processing of massive amounts of data. Cadence's Mellacheruvu Srikanth finds that verifying all the new features and enhancements across several generations of PCIe while maintaining backwa... » read more

Blog Review: Jan. 24


Siemens' John McMillan finds that while 3D-IC capabilities are ready for mainstream, mass adoption success depends on how easily, effectively, and efficiently a solution can be delivered and points to five workflow adoption focus areas. Cadence's Andre Baguenie shows how to easily convert a logic signal to an electrical value using Verilog-AMS and the transition filter. Synopsys' Chris Cl... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan Synopsys will acquire Ansys for about $35 billion in cash and stock. The deal will boost Synopsys' multi-physics simulation capabilities, which are essential for complex 3D-IC designs, where thermal density can have significant repercussions. The acquisition is expected to be finalized in the first half of 2025. Worldwide semiconductor revenue ... » read more

Blog Review: Jan. 17


Cadence's Rajneesh Chauhan introduces the Back-Invalidate feature in Compute Express Link (CXL) 3.0 and how it contributes to the efficient functioning of modern data center architectures by upholding cache coherence across multiple hosts and devices. Synopsys' Brett Murdock and Dana Neustadter point out the importance of protecting against DRAM attacks such as Rowhammer, RAMbleed, and cold-... » read more

Which Data Works Best For Voltage Droop Simulation


Experts at the Table: Semiconductor Engineering sat down to talk about the need for the right type of data, why this has to be done early in the design flow, and how 3D-IC will affect all of this, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, prod... » read more

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