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Week In Review: Auto, Security, Pervasive Computing


Pervasive computing — IoT, edge, cloud, data center, and back Arm announced its Armv9 architecture, which is designed for secure, pervasive computing that can run in more types of AI systems. Because most data will be touching an Arm-based chip in the near future — whether on the edge, IoT, or data center — Arm enhanced the security, in addition to improving performance and AI/ML capabil... » read more

Aging Analysis Common Model Interface Gains Momentum


By Greg Curtis, Ahmed Ramadan, Ninad Pimparkar, and Jung-Suk Goo In February 2019, Siemens EDA wrote an article1 entitled “The Time Is Now for a Common Model Interface”. Since that time, we have continued to see increasing demand for aging analysis, not only in the traditional automotive space, but also in other areas of technology design, such as mobile communication and IoT application... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Micron will cease development of 3D XPoint, a next-generation memory technology. Micron also plans to sell a fab that produces 3D XPoint chips. For some time, Intel and Micron have co-developed 3D XPoint, which is based on phase-change memory technology. Intel sells solid-state storage drives (SSDs) using 3D XPoint. In a fab located in Utah, Micron is producing this memo... » read more

Week In Review: Design, Low Power


Qualcomm finalized its acquisition of data center chip startup Nuvia with a price of $1.4 billion. Nuvia is working on a data center SoC and Arm-based CPU core it claims will lower performance per total cost of ownership by matching high performance with high efficiency and limiting maximum power to that which can be dissipated in an air-cooled environment. Qualcomm said Nuvia’s technology wo... » read more

Week In Review: Manufacturing, Test


Government policy For the last four years, the U.S. and China have been embroiled in a trade war, especially on the technology front. The U.S. has implemented a number of export control measures and tariffs in the arena. But there might be a thawing in the tense relationship between the two superpowers. “Reports surfaced Thursday indicating the China Semiconductor Industry Association (CSIA)... » read more

Week In Review: Design, Low Power


Tools & IP Codasip unveiled three commercially licensed add-ons to the Western Digital SweRV Core EH1, aiming to allow it to be designed into a wider range of applications. The SweRV Core EH1 is a 32-bit, dual-issue, RISC-V ISA core with a 9-stage pipeline, open-sourced through CHIPS Alliance. The add-ons offer a floating-point unit (FPU) that supports the RISC-V single precision [F] and d... » read more

An Integrated Approach To Power Domain And CDC Verification


Reducing power consumption is essential for both mobile and data center applications. Yet it is a challenge to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification validates only the functional correctness of power... » read more

Blog Review: March 10


Siemens EDA's Harry Foster checks out how the maturity of verification processes impact bug escapes in FPGA designs and whether safety critical development processes prevent bugs from escaping to silicon. Synopsys' Dennis Kengo Oka examines the weaknesses and vulnerabilities in automotive keyless entry systems and how security researchers hacked the Tesla Model X key fob. Cadence's Paul M... » read more

Over-the-Air Automotive Updates


Modern vehicles are increasingly-connected devices with growing volumes of electronic systems. This systemic complexity means that even an average vehicle design will include over 150 ECUs, which control not just infotainment and communications, but powertrain, safety, and driving systems (figure 1). We see not just a surge in the volume and complexity of electronic hardware, but also software.... » read more

Blog Review: March 3


Siemens EDA's Ray Salemi considers incrementalism in engineering, the transition from drawing circuits to writing RTL, and the next big leap of using proxy-driven testbenches written in Python. Cadence's Shyam Sharma looks at key changes from LPDDR5 in the LPDDR5X SDRAM standard, which extends clock frequencies to include 937MHz and 1066MHz resulting in max data rates of 7500MT/s and 8533 MT... » read more

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