Chip Industry Week In Review


Around the world South Korea unveiled a sweeping AI and semiconductor investment drive, planning three mega projects that tie semiconductors, physical AI/robotics, and AI data centers into a single industrial plan, with government support for regional chip clusters, packaging capacity, power, water, sites, and workforce development. Among the new investments: Samsung will spend $260B on n... » read more

Blog Review: June 17


Cadence's Rajan Jani explains NVMe's Controller Memory Buffer feature, which exposes on-controller memory directly to the host system to reduce latency, improve PCIe fabric efficiency, and increase performance in multi-switch topologies. Siemens' Linus Tauro shares how to run an SSN datapath at double the I/O data rate by implementing a BusFrequencyMultiplier and BusFrequencyDivider pair. ... » read more

Chip Industry Week In Review


Computex in Taiwan: Arm and Nvidia introduced an AI PC platform, RTX Spark, with an Arm-based Grace CPU, Blackwell RTX GPU, and unified memory. Cadence announced a fully autonomous virtual agentic AI design engineer, enabling customers to run dynamic simulations in automated workflows. Intel launched Xeon 6+, its first data-center CPU built on Intel Foundry's 18A process. The company... » read more

AI-Defined Vehicles Increase Pressure On Auto Ethernet Reliability


Key Takeaways: For AI-defined vehicles and onboard agentic AI, Automotive Ethernet provides high bandwidth for sensor data fusion, TSN ensures low latency and synchronization for real-time decisions, and MACsec secures the data link. Time-sensitive networking (TSN) is an essential protocol for ensuring 10BASE-T1S delivers data to where it needs to go on time. Still, it becomes less esse... » read more

Chip Industry Week In Review


ECTC Panel-level packaging, hybrid bonding, new substrates, and fine-pitch interconnects topped the list of advanced packaging technologies at ECTC this week. Among the announcements: ASE launched an automated 310mm × 310mm panel-level packaging production line. Expected to enter production in the first half of 2027, the line is compatible with FOCoS and FOCoS-Bridge pa... » read more

Chip Industry Week In Review


Advanced nodes and packaging AMD announced more than $10B in Taiwan ecosystem investments to scale advanced packaging manufacturing for AI infrastructure. The effort includes EFB-based 2.5D packaging collaborations with ASE and others. AMD also announced the start of its production ramp of its Venice processors on TSMC's 2nm process. Lam Research established a panel-level packaging cen... » read more

Chip Industry Week in Review


Global The U.S. created a licensing path for Nvidia H200 shipments in January and has since approved sales to 10 Chinese companies, but so far no shipments have been confirmed, reports Reuters. With a looming end-of-year expiration, SIA, SEMI, and other business groups are urging Congress to extend the US semiconductor tax credit and expand it to cover semiconductor design and other act... » read more

Blog Review: May 13


Siemens' Loay Hegazy, Mohamed Taher, and Sherif Hammouda describe a GPU rasterizer designed specifically for computational lithography and present benchmark results and practical implications for mask synthesis workflows. Cadence's Udaya Shankar introduces RTL, logic, and physical restructuring techniques and how they can help improve PPA, reduce dynamic power consumption, and optimize place... » read more

AI Accelerator Testing Depends On DFT Innovations


Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

Debugging Modern SoCs With Embedded Analytics: Instrumentation, Trace, And Faster Root-Cause Isolation


As SoCs chase ever higher performance and power efficiency, their designs have become harder to rootcause and harder to debug. Today’s devices combine billions of transistors with heterogeneous compute blocks and a growing mix of third‑party IPs, so failures can come from anywhere: a corner-case interaction between cores, an integration mistake, a timing assumption that no longer holds, or ... » read more

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