Digital IC Bring-Up With A Bench-Top Environment

The process of test pattern bring-up, debug, and device characterization is ripe for improvement.


One of the hottest markets for IC today is artificial intelligence (AI). The designs for AI chips are also among the largest and most complex, with billions of transistors, thousands of memory instances, and complex design-for-test (DFT) implementations with unique bring up and debug requirements. At this point, the volume of new AI chips is relatively low, but time-to-market is of paramount importance. Design teams need to save time anywhere they can, and the process of test pattern bring-up, debug, and device characterization is ripe for improvement.

After manufacturing, test patterns must be validated against the silicon before performing full manufacturing test. Typically, this involves converting the test patterns to a tester-specific format and generating a test program that will be executed by automatic test equipment (ATE). When any of these patterns fail, the ATE output is then translated into chip failure data and processed by diagnosis tools. This is inefficient for several reasons:

  • It requires time on the ATE, which can be expensive and hard to reserve
  • It involves several disconnected teams— the product engineers, DFT engineers, and the physical failure analysis team
  • When reverse-mapping failure data from the chip level to the core level, there is often a lack of diagnosis information

This standard silicon bring-up flow is becoming unwieldy but can be significantly improved by using commercial EDA software instead of ATE to run the test patterns. A desktop system greatly reduces the need for expensive tester equipment in the test pattern bring-up process since all the debug and device characterization can be done anywhere. The result is significantly reduced cycle time, better management of cross-functional teams, and more efficient failure diagnosis.

Such a desktop silicon bring-up system (Figure 1) includes a computer with a USB-to-digital adaptor connected to a bring-up/validation board with the device under test (DUT). For many designs, a validation board is created to facilitate software development and other bring-up applications. The board is typically set up to emulate the conditions present during test on an ATE (such as the power supply pins, clocks, tied pins, etc.), and with all pins required for testing available for the USB-to-digital adaptor. Several different adaptors can be used, depending on pin count and I/O voltage requirements. Optionally, GPIB-programmable power supplies and clock generators can be used to automate device characterization.

Figure 1. A bench setup for silicon bring-up. A computer running Tessent SiliconInsight, the validation board with USB adaptor, a power supply, and a clock generator.

Comparable commercially available setups are limited to BIST and other test instruments accessed exclusively through the DUT’s JTAG port. This new system expands the scope to non-JTAG test access and a much wider range of pattern applications and diagnosis routines. For instance, ATPG patterns with-chip compression and over 25 external scan channels can be tested and diagnosed with the push of a button.

The software that executes the test patterns then collects and analyzes the fail data is built the same DFT software platform used to create the test structures and generate the test patterns. This common platform makes it possible for the software to understand how all the test structures and protocols work so that the results can be provided in a meaningful fashion. When test patterns fail during silicon bring-up, you are typically interested in determining which scan cells capture the failing data. In the presence of on-chip compression and hierarchical DFT, complex decoding and dedicated diagnosis patterns may be required. With this new system, the complex mapping and generation of dedicated diagnosis patterns is now done under the hood, significantly simplifying the debug process.

Another feature of the desktop silicon debug process is that it can include design layout information (in the form of LEF and DEF files), which eases the debug process by locating the fault in the layout. The same methodology can also be used for silicon characterization such as checking the variation in performance depending on clock speed and voltage.

This bench-top flow (Figure 2) greatly reduces the time for silicon test pattern bring-up and debug.

Figure 2. Bench-top silicon bring-up flow.

This system is already being used successfully by large companies and also by AI chip startups. At the 2016 IEEE Workshop on Defects, Adaptive Test, Yield, and Data Analysis (DATA 2016), Cypress Semiconductor described how the system was used to bring up a touchscreen controller chip (Figure 3). The chip had on-chip EDT scan compression with four scan channels that can be connected to a tester for the application of compressed ATPG patterns.

An Opal Kelly XEM6310 USB-to-digital adaptor was connected via USB to a laptop running the Mentor Tessent SiliconInsight software. A simple configuration file indicating which adaptor was used and the pin map was used to set up the software for this particular DUT.

Figure 3. The hardware setup described in the DATA 2016 presentation.

The failing cycle data was automatically collected by the tool during the execution of the ATPG pattern set and used along with the design information to diagnose failing suspects. In this experiment, the results pointed to two failing flops in a scan chain. The user was able to isolate the failing flops and generate a new ATPG pattern set with the faulty chain masked. When this modified pattern set was applied to the DUT, the test passed with no failing cycles.

The user was also able to diagnose the root cause of the silicon failure based on the identified failure location using this flow. Finding the root cause could have been done in a conventional bring-up setup, but it would require a separate test insertion and access to the expensive ATE equipment for silicon bring-up and debug. Using the desktop flow accelerated the process significantly.

Saving time in the chip design flow is important for companies in highly competitive segments, such as AI. Using a desktop system for test pattern bring-up, debug, and diagnosis can reduce the time required in this phase by between 50% and 80% while improving the process diagnosing IC failures. The desktop test pattern bring-up system accelerates debug and characterization and reduces the cycle time.

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