The Single Best DFT Move You Can Make


A proven method to simplify a complex problem is to break it into smaller chunks. In the case of today’s large, complex SoCs, this means using hierarchical methods to design the blocks, then combine the results at the top level. While this sounds obvious, it hasn’t always been practical or technologically feasible to perform some tasks, like DFT, at the block level and translate that work s... » read more

BiST Grows Up In Automotive


Test concepts and methods that have been used for many years in traditional semiconductor and SoC design are now being leveraged for automotive chips, but they need to be adapted and upgraded to enable monitoring of advanced automotive systems during operation of a vehicle. Automotive and safety critical designs have very high quality, reliability, and safety requirements, which pairs pe... » read more

Tessent Hierarchical ATPG Reference Flow for Arm Cortex-A75


Arm and Mentor have jointly developed a reference flow for a hierarchical DFT and ATPG implementation with Tessent for any Arm subsystem based on Cortex A-series IP. The reference flow, described in this paper, provides documentation, seamless interfaces, and scripts that accelerate the implementation of a hierarchical test solution. Arm and Mentor are dedicated to enabling customer success, re... » read more

Smart Plug-And-Play DFT For Arm Cores


Modern SoCs are experiencing continued growth in capabilities and design sizes with more and more subsystem IPs being implemented. These large, complex, multi-core SoCs need strategies for DFT and ATPG that effectively reduce DFT effort, minimize ATPG runtime, and still achieve the target test coverage. Hierarchical DFT enables designing and testing of these designs in a systematic and repeatab... » read more

Meeting ISO 26262 Requirements Using Tessent IC Test Solutions


As the industry moves towards greater automation in vehicles, suppliers of the ICs used to drive the automotive electronic systems are rapidly adopting solutions to meet ISO 26262 requirements. The Tessent family of IC test products offers the highest defect coverage, in-system non-destructive memory test, hybrid ATPG/Logic BIST, and analog test coverage measurement. These technologies add up t... » read more

The Week In Review: Design


M&A GlobalFoundries formed Avera Semiconductor, a wholly-owned subsidiary focused on custom ASIC designs. While Avera will use its relationship with GF for 14/12nm and more mature technologies, it has a foundry partnership lined up for 7nm. The new company's IP portfolio includes high-speed SerDes, high-performance embedded TCAMs, ARM cores and performance and density-optimized embedded SR... » read more

Tessent Cell-Aware Test


Tessent Cell-Aware ATPG is a transistor-level ATPG-based test methodology that achieves significant quality and efficiency improvements by directly targeting specific shorts; opens and transistor defects internal to each standard cell; resulting in significant reductions in defect (DPM) levels. Traditional scan patterns are created using fault models that are based on the logical operation of t... » read more

Digital IC Bring-Up With A Bench-Top Environment


One of the hottest markets for IC today is artificial intelligence (AI). The designs for AI chips are also among the largest and most complex, with billions of transistors, thousands of memory instances, and complex design-for-test (DFT) implementations with unique bring up and debug requirements. At this point, the volume of new AI chips is relatively low, but time-to-market is of paramount im... » read more

The 2017 International Test Conference


Machine learning is a hot topic at many technical conferences this year. It will be true at the upcoming International Test Conference, which opens near the end of this month in Fort Worth, Texas. On Sunday, October 29, there are two tutorials devoted to machine learning. Monday, October 30, will have one tutorial related to the topic. The conference gets fully under way on Halloween, wit... » read more

Fault Simulation Reborn


Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the quality of manufacturing test vectors. That task was replaced almost entirely by [getkc id="173" comment="scan test"] and automatic test pattern generation (ATPG). Today, functional safety is cau... » read more

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