Alex Burlak

  (all posts)
Alex Burlak is vice president of test and analytics at proteanTecs. Before joining the company, Burlak held senior director of interconnect and silicon photonics product engineering positions at Mellanox. He holds a B.Sc. in Electrical Engineering from The Israel Institute of Technology, Technion.

Author's Latest Posts

Critical Optimization Factors For GenAI Chipmakers
By Alex Burlak - 14 Oct, 2025 - Comments: 0

Today’s GenAI arms race is fought with novel chip architectures and packaging. Specialized hardware designs are proliferating in the form of GPUs, TPUs, NPUs, and more, all tuned for parallelism and matrix-heavy AI math. In this hyper-competitive landscape, chip vendors scramble to differentiate their products on multiple fronts. They promise some mix of better performance, efficiency, or ... » read more

The Painful Reality Of Scaling Cloud AI
By Alex Burlak - 12 Aug, 2025 - Comments: 0

The shift to Generative AI (GenAI) has overwhelmed existing infrastructure, transforming previously rare issues into daily operational realities. Skyrocketing costs, intense energy consumption, and hardware failures at unprecedented scales illustrate the strain of current AI workloads. With models like GPT-4 costing tens of millions and GPT-5 projected to surpass a billion-dollar threshold, the... » read more

GenAI’s Breakneck Pace Is Reshaping The Semiconductor Industry
By Alex Burlak - 10 Jul, 2025 - Comments: 0

Humankind is witnessing a technological revolution so extreme that its full magnitude might extend beyond the scope of our intellect. Generative AI (GenAI) is doubling its performance every six months [1], outpacing Moore's law in what the industry calls Hyper Moore's Law. Some cloud AI chipmakers expect to double or triple performance every year for the next ten years [2]. In this three-part b... » read more

Can Your ATPG Do This? Cut Defects Escaping Detection With ML
By Alex Burlak - 10 Jun, 2025 - Comments: 0

Chipmakers worldwide consider Automatic Test Pattern Generation (ATPG) their go-to method for achieving high test coverage in production. ATPG generates test patterns designed to detect faults in the silicon and ensures they are applied effectively using the chip’s Design-for-Test (DFT) infrastructure. This combination enhances fault detection while optimizing test efficiency. These patter... » read more

No Two Chips Are Alike
By Alex Burlak - 27 Jul, 2020 - Comments: 0

As semiconductor processes continue to shrink it’s becoming increasingly challenging to manage the parameters of individual devices not only across the diameter of the wafer, but also across the length of a single chip, especially for a complex chip with a large area. Today’s standard approach to this problem is to assume the worst case and to create a sub-optimal design that accommodates t... » read more

Using Machine Learning To Gain Data Insights
By Alex Burlak - 11 Feb, 2020 - Comments: 0

Today’s consumers have little appetite for networks that go down, for electronic devices that fail, and for any kind of digital service that doesn’t deliver as promised every time. Reliability is no longer a nice-to-have. It's  a key feature. The continued scaling of advanced electronics and chip manufacturing technologies, however, makes reliability harder to achieve — even as expectati... » read more

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