Blog Review: Dec. 17

Cadence’s Shyam Sharma checks out what’s new in the latest Open NAND Flash Interface 5.2 standard, including a Separate Command Address protocol that allows Hosts to optimize the command and data scheduling to increase overall available bandwidth.

Siemens’ Kyle Fraunfelter and Melville Bryant contend that improving semiconductor manufacturing and fab sustainability starts with a digital twin that mirrors how the actual manufacturing processes and systems behave in real time to predict production performance and optimize operations without disrupting live production.

Synopsys’ Greg Sorber looks at Fujitsu’s newest data center chip and how its new processor architecture was designed to support high-performance workloads while providing 40% energy savings compared to current data centers.

Arm’s Éliás Bálint introduces an open-source image processing language designed to streamline performance without sacrificing readability by defining image processing logic separately from hardware-specific optimization strategies, so changes to how computations are executed do not require rewriting the algorithm itself.

Keysight’s Colin Bauer shares highlights from the Brooklyn 6G Summit, including the changing dynamic between uplink and downlink traffic and the growing importance of digital twins and high-quality datasets in shaping AI-driven wireless networks.

Ansys’ Balavignesh Vemparala considers how AI will augment physics simulation by reducing numerical effort, streamlining repetitive setup and reporting work, and widening the design space that can be explored within a given budget.

ESD Alliance’s Bob Smith chats with Maheen Hamid of Breker Verification Systems about tracking trends in the semiconductor industry and how RISC-V is driving collaboration in verification.

And don’t miss the blogs featured in the latest Automotive, Security & Emerging Technologies, Test, Measurement & Analytics, and Low Power-High Performance newsletters:

Siemens’ Matt Walsh digs into why design enablement is now mission-critical for automotive and secure systems.

Rambus’ Scott Best warns that sensitive data must be protected when moving between CPU and memory.

Keysight’s Mafalda Monteiro Oliveira Cortez explains what manufacturers need to know to comply with upcoming EU cybersecurity regulations.

Infineon’s Akshara Arun details how a structured IoT communication approach overcomes data collisions, inefficiencies, and delays.

Synaptics’ Vikram Gupta points to the need for a purpose-built, AI-native approach that integrates hardware and software right from the foundational design.

Cadence’s Veena Parthan shows how CFD can pinpoint the optimal configuration for passive noise mitigation in industrial fans.

Imagination’s Eleanor Brash checks out how cloud gaming profitability depends on maximizing concurrent users per GPU while maintaining a premium user experience.

PDF Solutions’ Bob Reback shows how cloud technologies, AI, and secure remote connectivity are shaping the future of manufacturing.

Onto Innovation’s Jiangtao Hu looks at measuring and monitoring gate profiles, film thickness, and structural uniformity at the nanometer scale.

Teradyne’s Alexander Metzdorf digs into flexible, future-ready test strategies for the irregular cycles of sensor design and standards development.

proteanTecs’ Ziv Paz details how in-situ visibility can be used to determine chip behavior under real cloud AI workloads and operating conditions.

Modus Test’s Jesse Ko explains how the health of test sockets impacts a production line.

Siemens’ Francisca Tan points to the benefits of non-intrusive observation and data collection to ensure the entire system behaves as expected.

Advantest’s Davette Berry explores cross-chip data path validation in multi-die packages and its impact on power, performance, and reliability.

Fraunhofer EAS’ Benjamin Prautsch argues that choosing the right problems for AI to tackle will be crucial for A/MS IC design.

Synopsys’ Monica Olvera and Gustavo Pimentel find that modern compute is pushing far more data than prior generations of I/O were designed for.

Quadric’s Lee Vick digs into how an ancient data point proves a modern transformation.

Rambus’ Simon Bussières looks at how to ensure robust, scalable, and secure data transport across heterogeneous sensor arrays.

Expedera’s Paul Karazuba explains how high utilization, low memory movement, and broad model compatibility can coexist in edge AI.

Cadence’s Reela Samuel breaks down how 3D-IC thermal constraints directly influence floor planning, macro placement, and power delivery network topology.

Arm’s Odin Shen investigates how CPU-based embedding, unified memory, and local retrieval workflows come together to enable responsive, private RAG pipelines on desktop AI platforms.

Ansys’ Scott Parent highlights how digital threads that connect every stage of a product’s lifecycle can enable seamless collaboration among technologies, departments, and stakeholders.

Siemens’ Kurt Takara suggests enhancing the reliability of multi-clock and safety-critical designs to minimize the risk of costly late-stage bugs.