Top Stories
Adaptive Test Gaining Ground For HPC And AI Chips
Real-time optimization is moving to the tester, but results are mixed so far.
Metrology Digs Deep To Produce Next-Generation 3D NAND
Deep vertical holes and re-entrant features challenge the best metrology methods.
Zero-Trust Data Sharing Architectures Redefining Chip Manufacturing
Collaboration becomes necessary at advanced nodes, but implementation can be painful.
Video
DFT Shifts Further Left
How multi-die assemblies are changing design for test.
Sponsor Blogs
PDF Solutions’ Bob Reback shows how cloud technologies, AI, and secure remote connectivity are shaping the future of manufacturing, in Tracing The Equipment Connectivity Journey.
Onto Innovation’s Jiangtao Hu looks at measuring and monitoring of gate profiles, film thickness, and structural uniformity at the nanometer scale, in Smaller Geometries, Bigger Demands: The Role Of OCD In GAA Logic And Vertical Gate DRAM Process Control.
Teradyne’s Alexander Metzdorf digs into flexible, future-ready test strategies for the irregular cycles of sensor design and standards development, in Invisible Interfaces: The Hidden Challenge Behind Every Great Image Sensor.
proteanTecs’ Ziv Paz details how in-situ visibility can be used to determine chip behavior under real cloud AI workloads and operating conditions, in Resilient And Optimized GenAI Systems.
Modus Test’s Jesse Ko explains how the health of test sockets impacts a production line, in Boosting Production Performance: Ensuring Only Known-Good Sockets Enter Your Line.
Siemens’ Francisca Tan points to the benefits of non-intrusive observation and data collection to ensure the entire system behaves as expected, in Beyond The Core: Tackling System-Wide Debugging For Complex SoCs.
Synopsys’ Srikanth Venkat Raman and Sri Ganta highlight left-shifting DFT, scalable tests from manufacturing to the field, and enabling system-level tests for in-field debug, in Scalable End-To-End Test Solutions For Today’s Complex SoCs.
Advantest’s Davette Berry explores cross-chip data path validation in multi-die packages and its impact on power, performance, and reliability, in Tackling Chip Complexity With Integrated System-Level Test Solutions.
Sponsor White Papers
Overview Of Radiation Dose During X-ray Inspection Of Electronics
The fundamental mechanism for radiation damage in semiconductor devices, and methods for reducing dose during X-ray inspection.
Enhancing CMP Process Control with Intelligent Line Monitoring & Integrated Metrology
As semiconductor manufacturers push the boundaries of performance and functionality—driven by high-performance computing and AI applications—chemical mechanical planarization (CMP) processes increase in intensity and complexity.
The Growing Need For Collaboration Across The Semiconductor Industry
Harness the vast amounts of IC manufacturing data, much of which was previously unanalyzed, to drive operational efficiency and innovation across internal and external operations.
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