PCIe 8.0: Preparing For The Next Doubling

By Monica Olvera and Gustavo Pimentel

Every few years, the industry confronts the same challenge: can general-purpose I/O double again without overwhelming power budgets, overwhelming signal-integrity limits, or fragmenting the ecosystem? With PCIe 8.0, the answer appears to be yes—if the entire stack continues to advance together. Public PCI-SIG information outlines an objective of 256.0 GT/s per lane and close to 1 TB/s bi-directional throughput on a x16 link, all while preserving the backward-compatibility that has defined PCIe from the start.

What’s publicly defined so far

Fig. 1: IO BW doubles every 3 years. Image from: PCI-SIG

PCI-SIG has highlighted 8.0 goals such as 256 GT/s signaling, connector and interconnect evaluations, updated latency/FEC and reliability targets, and protocol refinements for more effective bandwidth. These efforts build on the PCIe 7.0 member release at 128 GT/s in June 2025, with development of PCIe 8.0 expected to progress toward 2028.

Why another doubling matters

Modern compute is pushing far more data than prior generations of I/O were designed for. AI training clusters, accelerated analytics, SmartNICs, and storage are routinely pushing today’s host‑to‑accelerator and accelerator‑to‑accelerator links to their limits. Crossing into terabyte‑per‑second territory for a single x16 interface helps rebalance both scale‑up pipelines inside a server (CPU↔GPU, GPU↔GPU, device↔device) and scale‑out links to high‑speed networks, where 800G/1.6T and future Ethernet generations demand host interfaces that do not become the bottleneck.

These shifts are not abstract. They shape topologies, rack layouts, network fabrics, memory‑pooling strategies, and overall system economics.

Doubling the bandwidth enables PCIe to continue to be a leading standard for in the box and in the rack links due to interoperability, reliability, and high quality PHYs enabling lower latency connections. This leverages existing infrastructure, and eases implementations with minimal risks for future deployments when compared to any alternative technologies.

The engineering hurdles ahead

Several technical fronts will define whether designs achieve PCIe 8.0 performance targets at practical power and cost:

• Channel reach and materials. Higher Nyquist frequencies tighten insertion‑loss budgets and make copper reach more challenging. PCB materials, connectors, via structures, and shorter internal traces become critical variables. Retimers are expected to be more widely used as speeds increase.
• Receiver complexity. The high‑speed community continues to evaluate MLSD‑class equalization methods to recover data on high‑loss channels. These techniques demand more computational depth inside the receiver but may be needed as eye openings shrink at 256 GT/s.
• Optical pathways. As copper approaches physical limits, optics becomes a realistic consideration for reach and topology needs. PCI‑SIG has noted that connector and interconnect updates are under review for 8.0 while maintaining backward compatibility.
• Latency and reliability. Workgroups are validating latency and FEC goals so real‑world throughput scales with the signaling rate—not just the theoretical maximum.

Why interoperability remains PCIe’s advantage

PCIe’s interoperability and compliance program is one of the primary reasons it succeeds across so many markets. At compliance workshops, devices must pass all mandatory tests, including electrical and protocol compliance, and at least 80% of interoperability tests—an approach that encourages early participation while ensuring ecosystem quality. These workshops will only grow in importance as companies begin evaluating PCIe 8.0 behavior across boards, channels, and system types.

Looking forward

In today’s fast-moving world of AI and HPC infrastructure, standards advancement matters—but so does proven ecosystem leadership. Synopsys isn’t just observing the evolution of PCIe, we’ve committed ourselves to be at its leading edge. Our PCIe 6.x IP solution was selected as the industry’s first official “Gold System” for PCIe 6.x compliance testing, providing a trusted reference platform for device interoperability and ecosystem readiness. In parallel, we introduced a complete PCIe 7.0 IP solution, including controller, PHY, IDE security module and verification IP, and delivered world-first demonstrations of PCIe 7.0 over optics and RC-to-endpoint links at 128 GT/s per lane.

As the industry transitions toward PCIe 8.0, we continue our commitments: participating actively in the PCI-SIG consortium, engaging in interoperability and compliance workshops, and enabling early-adopter programs that anticipate tomorrow’s bandwidth needs. Recently, we demonstrated 256 GT/s data transmission using existing silicon in our labs, showcasing the feasibility of PCIe 8.0 data-rates. This milestone highlights our ability to deliver high-speed PAM4 signaling with exceptional eye quality, proving readiness for next-gen bandwidth demands.

Fig. 2: Synopsys IP running at 256 GT/s.

With decades of interface IP experience and broad ecosystem cooperation, our goal remains the same: help customers adopt standards confidently, integrate interoperably, and reach first-pass silicon success. To explore today’s PCIe solutions and prepare your next-gen designs, visit the Synopsys PCIe IP page.

Gustavo Pimentel is a principal product manager at Synopsys.