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HBM3 In The Data Center


Frank Ferro, senior director of product management at Rambus, talks about the forthcoming HBM3 standard, why this is so essential for AI chips and where the bottlenecks are today, what kinds of challenges are involved in working with this memory, and what impact chiplets and near-memory compute will have on HBM and bandwidth.     » read more

Novel In-Pixel-in-Memory (P2M) Paradigm for Edge Intelligence (USC)


A new technical paper titled "A processing-in-pixel-in-memory paradigm for resource-constrained TinyML applications" was published by researchers at University of Southern California (USC). According to the paper, "we propose a novel Processing-in-Pixel-in-memory (P2M) paradigm, that customizes the pixel array by adding support for analog multi-channel, multi-bit convolution, batch normaliza... » read more

Review of Bumpless Build Cube Using Wafer-on-Wafer & Chip-on-Wafer for Tera-Scale 3D Integration


New research paper titled "Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)" from researchers at Tokyo Institute of Technology and others. Abstract "Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bum... » read more

Automotive Bandwidth Issues Grow As Data Skyrockets


Bandwidth requirements for future vehicles are set to explode as the amount of data moving within vehicles, between vehicles, and between vehicles and infrastructure, continues to grow rapidly. That data will be necessary for a variety of functions, some of which are here today and many of which are still in development. On the safety side, that includes everything from early warning systems... » read more

Measuring Frequency Dependence Across 5G mmWave Bands (NIST)


New research paper from NIST, "Methodology for Measuring the Frequency Dependence of Multipath Channels Across the Millimeter-Wave Spectrum." Abstract "Millimeter-wave (mmWave) communications promise Gigabit/s data rates thanks to the availability of large swaths of bandwidth between 10–100 GHz. Although cellular operators prefer the lower portions of the spectrum due to popular belief ... » read more

1.6 Tb/s Ethernet Challenges


Moving data at blazing fast speeds sounds good in theory, but it raises a number of design challenges. John Swanson, senior product marketing manager for high-performance computing digital IP at Synopsys, talks about the impact of next-generation Ethernet on switches, the types of data that need to be considered, the causes of data growth, and the size and structure of data centers, both in the... » read more

HBM3: Big Impact On Chip Design


An insatiable demand for bandwidth in everything from high-performance computing to AI training, gaming, and automotive applications is fueling the development of the next generation of high-bandwidth memory. HBM3 will bring a 2X bump in bandwidth and capacity per stack, as well as some other benefits. What was once considered a "slow and wide" memory technology to reduce signal traffic dela... » read more

Leaky Buddies: Cross-Component Covert Channels on Integrated CPU-GPU Systems


Find Technical Paper link here. Abstract: "Graphics Processing Units (GPUs) are ubiquitous components used across the range of today’s computing platforms, from phones and tablets, through personal computers, to high-end server class platforms. With the increasing importance of graphics and video workloads, recent processors are shipped with GPU devices that are integrated on the same chi... » read more

Streaming Scan Network


The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. In the traditional approach to delivering scan test data to cores, each core requires a dedicated connection to chip-level pins, which doesn’t allow for much flexibility, as the dependencies betwee... » read more

Next-Gen SerDes Roadmap


An explosion in data is causing a series of successive bottlenecks in the data center. Priyank Shukla, product marketing manager for high-speed SerDes IP at Synopsys, digs into the performance roadmap for moving data within server racks and between different racks, where the bottlenecks are today, and how they will be addressed in the future. Related SerDes Knowledge Center Top stories... » read more

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