High-Speed Signaling Drill-Down


Chip interconnect standards have received a lot of attention lately, with parallel versions proliferating for chiplets and serial versions moving to higher speeds. The lowliest characteristic of these interconnect schemes is the physical signaling format. Having been static at NRZ (non-return-to-zero) for decades, change is underway. “Multiple approaches are likely to emerge,” said Brig ... » read more

Design For Narrowband IoT


Most low-power chips are designed with the assumption that batteries can be recharged or replaced, but there is a whole set of IoT devices under development that are expected to be always-on, communicate over a cellular infrastructure, and remain functional on a coin-sized lithium-ion battery for a decade or more. Welcome to the world of Narrowband IoT (NB-IoT), a 3GPP standard (also known a... » read more

Rising Packaging Complexity


Synopsys’ Rita Horner looks at the design side of advanced packaging, including how tools are chosen today, what considerations are needed for integrating IP while maintaining low latency and low power, why this is more complex in some ways than even the most advanced planar chip designs, and what’s still missing from the tool flow. » read more

Choosing Between CCIX And CXL


Semiconductor Engineering sat down to the discuss the pros and cons of the Compute Express Link (CXL) and the Cache Coherent Interconnect for Accelerators (CCIX) with Kurt Shuler, vice president of marketing at Arteris IP; Richard Solomon, technical marketing manager for PCI Express controller IP at Synopsys; and Jitendra Mohan, CEO of Astera Labs. What follows are excerpts of that conversati... » read more

Last-Level Cache


Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources. » read more

New Ways To Optimize Machine Learning


As more designers employ machine learning (ML) in their systems, they’re moving from simply getting the application to work to optimizing the power and performance of their implementations. Some techniques are available today. Others will take time to percolate through the design flow and tools before they become readily available to mainstream designers. Any new technology follows a basic... » read more

HBM Issues In AI Systems


All systems face limitations, and as one limitation is removed, another is revealed that had remained hidden. It is highly likely that this game of Whac-A-Mole will play out in AI systems that employ high-bandwidth memory (HBM). Most systems are limited by memory bandwidth. Compute systems in general have maintained an increase in memory interface performance that barely matches the gains in... » read more

High-Performance Memory For AI And HPC


Frank Ferro, senior director of product management at Rambus, examines the current performance bottlenecks in high-performance computing, drilling down into power and performance for different memory options, and explains what are the best solutions for different applications and why. » read more

Brighter Future For Photonics


Photons increasingly are taking over where electrons are failing in communications, but mixing the two never has been easy. There always have been two potential implementation paths — building each on its own substrate and then stacking them, or building them on a single substrate. The tradeoff between the two solutions is more complex than it may initially appear, and ongoing improvements... » read more

Tradeoffs In Embedded Vision SoCs


Gordon Cooper, product marketing manager for embedded vision processors at Synopsys, talks with Semiconductor Engineering about the need for more performance in these devices, how that impacts power, and what can be done to optimize both prior to manufacturing. » read more

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