Manufacturing Bits: Oct. 12


MoSi2 pellicles for EUV Hanyang University has presented a paper that describes a novel molybdenum disilicide (MoSi2) pellicle membrane for use in extreme ultraviolet (EUV) lithography. With a 28nm thickness, a MoSi2 membrane has demonstrated a 89.33% transmittance for EUV lithography. The pellicle technology is still in R&D. MoSi2, which is a silicide of molybdenum, is a refractory cer... » read more

Manufacturing Bits: Oct. 6


High-NA EUV mask materials A team of researchers have presented a new paper on the tradeoffs of photomask absorber materials for high-NA extreme ultraviolet (EUV) lithography. In the paper, researchers concluded that the industry will likely require an alternative mask absorber stack for high-numerical aperture (high-NA) EUV lithography. Fraunhofer, Imec, ASML and Zeiss contributed to the... » read more

eBeam Initiative Surveys Report Upbeat Photomask Market Outlook


Every year, the eBeam Initiative conducts surveys that provide valuable insight into the key trends that are shaping the semiconductor industry. This year, industry luminaries representing 42 companies from across the semiconductor ecosystem participated in the 2020 eBeam Initiative Luminaries survey. 89% of respondents to the survey predict that photomask (mask) revenues in 2020 will stay the ... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs NXP has announced the grand opening of its 150mm (6-inch) RF gallium nitride (GaN) fab in Chandler, Ariz. This is said to be the most advanced fab dedicated to 5G RF power amplifiers in the United States. NXP’s new Chandler-based GaN fab is qualified now, with initial products ramping in the market and expected to reach full capacity by the end of 2020. GaN, a III-V techn... » read more

Manufacturing Bits: Aug. 10


EUV mask cleaning process TSMC has developed a new dry-clean technology for photomasks used in extreme ultraviolet (EUV) lithography, a move that appears to solve some major problems in the fab. TSMC and Samsung are in production with EUV lithography at advanced nodes, but there are still several challenges with the photomasks and other parts of the technology. Using 13.5nm wavelengths, EUV... » read more

Next Challenge: Parts Per Quadrillion


Requirements for purity of the materials used in semiconductor manufacturing are being pushed to unprecedented — and increasingly unprovable — levels as demand for reliability in chips over increasingly longer lifetimes continues to rise. And while this may seem like a remote problem for many parts of the supply chain, it can affect everything from availability of materials needed to make t... » read more

The Race To Much More Advanced Packaging


Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

Semicon West Day One/Two


For years, the semiconductor and equipment industry has congregated at the annual Semicon West trade show in San Francisco. It’s an event to get an update on the latest equipment, test and packaging technologies. It’s also a good way to meet with people who you haven’t seen in a year, if not longer. It’s a great way to get a pulse on the industry. Needless to say, Semicon is a vir... » read more

Manufacturing Bits: July 21


Intel’s next-gen MRAM At the recent 2020 Symposia on VLSI Technology and Circuits, Intel presented a paper on a CMOS-compatible spin-orbit torque MRAM (SOT-MRAM) device. Still in R&D, SOT-MRAM is a next-generation MRAM designed to replace SRAM. Generally, processors integrate a CPU, SRAM and a variety of other functions. SRAM stores instructions that are rapidly needed by the processo... » read more

Manufacturing Bits: July 14


Complementary FETs At the recent 2020 Symposia on VLSI Technology and Circuits, Imec presented a paper on a 3D complementary field-effect transistor (CFET) made on 300mm wafers. As a demonstration vehicle, Imec showed a CFET based on a 14nm process. Ideally, though, CFETs are next-generation transistors that are targeted for the 1nm node in the future. On the transistor front, chipmaker... » read more

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