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Breaking The 2nm Barrier


Chipmakers continue to make advancements with transistor technologies at the latest process nodes, but the interconnects within these structures are struggling to keep pace. The chip industry is working on several technologies to solve the interconnect bottleneck, but many of those solutions are still in R&D and may not appear for some time — possibly not until 2nm, which is expected t... » read more

FeFETs Bring Promise And Challenges


Ferroelectric FETs (FeFETs) and memory (FeRAM) are generating high levels of interest in the research community. Based on a physical mechanism that hasn’t yet been commercially exploited, they join the other interesting new physics ideas that are in various stages of commercialization. “FeRAM is very promising, but it's like all promising memory technologies — it takes a while to get b... » read more

Week In Review: Manufacturing, Test


Chipmakers The U.S. Semiconductor Industry Association (SIA) and several chip executives have sent a joint letter to President Biden, urging the administration to include substantial funding for semiconductor manufacturing and research in the U.S. As reported, the share of global semiconductor manufacturing capacity in the U.S. has decreased from 37% in 1990 to 12% today. “Semiconductors pow... » read more

DRAM’s Persistent Threat To Chip Security


A well-known DRAM vulnerability called "rowhammer," which allows an assailant to disrupt or take control of a system, continues to haunt the chip industry. Solutions have been tried, and new ones are being proposed, but the potential for a major attack persists. First discovered some five years ago, most of the efforts to eliminate the "rowhammer" threat have done little more than mitigate t... » read more

Manufacturing Bits: Feb. 2


Capacitor-less DRAM At the recent 2020 International Electron Devices Meeting (IEDM), Imec presented a paper on a novel capacitor-less DRAM cell architecture. DRAM is used for main memory in systems, and today’s most advanced devices are based on roughly 18nm to 15nm processes. The physical limit for DRAM is somewhere around 10nm. DRAM itself is based on a one-transistor, one-capacito... » read more

New Transistor Structures At 3nm/2nm


Several foundries continue to develop new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production is going to be difficult and expensive. Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s finFET transistors to new gate-all-around field-effect trans... » read more

Imec’s Plan For Continued Scaling


At IEDM in December, the opening keynote (technically "Plenary 1") was by Sri Samevadam of Imec. His presentation was titled "Towards Atomic Channels and Deconstructed Chips." He presented Imec's view of the future of semiconductors going forward, both Moore's Law (scaling) and More than More (advanced packaging and multiple die). It is always interesting to hear Imec's view of the world since... » read more

The Darker Side Of Hybrid Bonding


With semiconductors, it's often things everyone takes for granted that cause the biggest headaches, and that problem is compounded when something fundamental changes — such as bonding two chips together using a process aimed at maximizing performance. Case in point: CMP for backend of the line metallization in hybrid bonding. While this is a mature process, it doesn't easily translate for ... » read more

AI And High-NA EUV At 3/2/1nm


Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

Manufacturing Bits: Nov. 25


Lidar-on-a-chip At the upcoming IEEE International Electron Devices Meeting (IEDM), Samsung will present a paper on the industry’s first single-chip lidar beam scanner. (Go to this link and then look for paper 7.2, “Single-Chip Beam Scanner with Integrated Light Source for Real-Time Light Detection and Ranging,” J. Lee et al, Samsung.) Lidar, or light imaging, detection, and ranging, ... » read more

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