tag: EDA

Addressing Pain Points In Chip Design
By Ed Sperling - 13 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx, Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Leveraging Data In Chipmaking
By Ed Sperling - 12 Nov, 2019 - Comments: 0

John Kibarian, president and CEO of PDF Solutions, sat down with Semiconductor Engineering to talk about the impact of data analytics on everything from yield and reliability to the inner structure of organizations, how the cloud and edge will work together, and where the big threats are in the future. SE: When did you recognize that data would be so critical to hardware design and manufact... » read more

Service Revenue Growing With Chip Complexity
By Ann Steffora Mutschler - 04 Nov, 2019 - Comments: 0

Rising complexity, new markets, and a shortage of in-house expertise are beginning to rekindle demand for services for the first time in nearly a decade. The semiconductor industry has been racing to design chips for a variety of new and existing applications, but they are facing challenges on a number of fronts: Leading-edge chips require new architectures due to a sharp reduction in s... » read more

Mary Jane Irwin Receives The Kaufman Award
By Paul McLellan - 10 Oct, 2019 - Comments: 0

Mary Jane Irwin just got back from a cruise around the Greek islands with her husband of 53 years to celebrate being the first woman to receive the Kaufman award. When I wrote my post The 2019 Kaufman Award Goes to Mary Jane Irwin about her receiving the awards last week, I mostly just used the boilerplate biographical information from the press release. But that's rather dry, so I called her u... » read more

Less Margin, More Respins, And New Markets
By Ed Sperling - 10 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx; Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Open ISAs Gaining Traction
By Ann Steffora Mutschler - 26 Sep, 2019 - Comments: 0

Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs. There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those archite... » read more

EDA Revenue Up 6.6% For Q2
By Ann Steffora Mutschler - 17 Sep, 2019 - Comments: 0

Highlighted by double digit growth in semiconductor IP and the Asia/Pacific region, EDA industry revenue increased 6.6% for Q2 2019 to $2,472.1 million, compared to $2,318.5 million in Q2 2018, according to the ESD Alliance Market Statistics Service. The four-quarters moving average, which compares the most recent four quarters to the prior four quarters, increased by 6%, which represented a... » read more

The Race For Better Computational Software
By Ed Sperling - 05 Sep, 2019 - Comments: 0

Anirudh Devgan, president of Cadence, sat down with Semiconductor Engineering to talk about computational software, why it's so critical at the edge and in AI systems, and where the big changes are across the semiconductor industry. What follows are excerpts of that conversation. SE: There is no consistent approach to how data will be processed at the edge, in part because there is no consis... » read more

IP’s Growing Impact On Yield And Reliability
By Ann Steffora Mutschler - 04 Sep, 2019 - Comments: 0

Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP. Utilizing poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to... » read more

Siemens-Mentor Deal Retrospective
By Ed Sperling - 21 Aug, 2019 - Comments: 1

Tony Hemmelgarn, president and CEO of Siemens PLM Software and CEO of Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about the acquisition of Mentor Graphics, the shift toward more customized design, and where AI fits into the design picture. SE: How does a company like Siemens see the EDA industry evolving? Hemmelgarn: Part of the reason we bought Mentor Grap... » read more

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