tag: EDA

Moore’s Law, Supply Chains And Security
By Brian Bailey - 16 Jan, 2020 - Comments: 0

The debate about the future of Moore's Law continues, while other parts of the industry look for alternatives. In between, supply chains are being pulled in multiple directions, with safety and security often in the middle. All across the semiconductor industry, significant changes are underway. Some of these have been in the works for some time. Others are new or accelerating faster than an... » read more

Bridging Math And Engineering In ML
By Ed Sperling - 08 Jan, 2020 - Comments: 0

Steve Roddy, vice president of products for Arm’s Machine Learning Group, examines the intersection of high-level mathematics in the data science used in machine learning within area, speed, and power limitations, and how to bring these two worlds together with the least amount of disruption. » read more

EDA, IP Growth Surge
By Ed Sperling - 07 Jan, 2020 - Comments: 1

EDA and IP grew 8.9% in Q3 of 2019, according to a just-released report, indicating continued confidence in semiconductor growth. Total revenue was up 8.9% globally compared with the same period in 2018, but that number is deceptively low. Revenue in China, for example, increased 5.7% compared to the same quarter in 2018, despite trade restrictions on sales of any IP developed in the United ... » read more

What Worked, What Didn’t In 2019
By Brian Bailey - 19 Dec, 2019 - Comments: 1

2019 has been a tough year for semiconductor companies from a revenue standpoint, especially for memory companies. On the other hand, the EDA industry has seen another robust growth year. A significant portion of this disparity can be attributed to the number of emerging technology areas for semiconductors, none of which has reached volume production yet. Some markets continue to struggle, a... » read more

OneSpin Users Gather in Munich
By Rob van Blommestein - 02 Dec, 2019 - Comments: 0

Even more than most other high-tech companies, EDA vendors rely on their users for many aspects of their success. Of course, customers provide the revenue that fuels the business, but their influence goes far beyond that. Many features in EDA tools, and even entire categories of products, arise from working closely with advanced users. Even before traditional Beta-testing, selected users provid... » read more

Better, Not Best
By Brian Bailey - 26 Nov, 2019 - Comments: 0

The semiconductor industry has been lulled into a particular way of thinking by Moore's Law. It is like the age-old joke — you don't have to outrun a bear, you only have to be faster than your companion. The same has held true for designs. There is little to no point being the best, you only have to be good enough to be better than the competition. That sets the bar. Best is also relative.... » read more

Thoroughly Verifying Complex SoCs
By Ann Steffora Mutschler - 26 Nov, 2019 - Comments: 0

The number of things that can go wrong in complex SoCs targeted at leading-edge applications is staggering, and there is no indication that verifying these chips will function as expected is going to get any easier. Heterogeneous designs developed for leading-edge applications, such as 5G, IoT, automotive and AI, are now complex systems in their own right. But they also need to work in conju... » read more

Portable Stimulus And Digital Twins
By Brian Bailey - 25 Nov, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Dave Kelf, chief marketing officer for Breker Verification Systems; Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemen... » read more

Is There A Crossover Point For Mainstream Anymore?
By Ed Sperling - 21 Nov, 2019 - Comments: 0

Until 28nm, it was generally assumed that process nodes would go mainstream one or two generations after they were introduced. So by the time the leading edge chips for smartphones and servers were being developed at 16/14nm and 10/7nm, it was assumed that developing a chip at 28nm would be less expensive, less complex, and that the process rule deck would shrink. That worked for decades. Th... » read more

Addressing Pain Points In Chip Design
By Ed Sperling - 13 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx, Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2020 SMG   |  Terms of Service  |  Privacy Policy