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EDA, IP Numbers In Record Territory


EDA and semiconductor IP revenue soared to a new high, up 17% worldwide in Q1 compared to the same period in 2020, with revenue in China surging 73%, according to new data from SEMI's Electronic System Design Alliance. For many financial reports outside of semiconductors, strong growth numbers can be misleading because they reflect comparatively weak earnings stemming from pandemic-related s... » read more

CEO Outlook: Chiplets, Longer IC Lifetimes, More End Markets


Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, longer IC lifetimes, and a spike in the number of end applications with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; an... » read more

Lower Power Chips: What To Watch Out For


Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues. With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, cos... » read more

Cell Library Verification Using Symbolic Simulation


Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models describing the cell functionality, schematic derived transistor level netlists, place and route views, physical layout views, post-layout extracted netlists as well as characterized timing and power m... » read more

Rocky Road To Designing Chips In The Cloud


EDA is moving to the cloud in fits and starts as tool vendors sort out complex financial models and tradeoffs while recognizing a potentially big new opportunity to provide unlimited processing capacity using a pay-as-you-go approach. By all accounts, a tremendous amount of tire-kicking is happening now as EDA vendors and users delve into the how and why of moving to the cloud for chip desig... » read more

Pitching To Your Audience


One of the most time-consuming parts of being a journalist is listening to enough people to get all sides of a story. Writing the story is often the easy part. What makes listening more difficult is that there are detail people and concept people, but few that sit in the middle. Some people love to get down into the details about the latest feature they have just implemented in a tool, or wh... » read more

CEO Outlook: More Data, More Integration, Same Deadlines


Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

An Advanced Infrastructure To Enable Secure, Cloud-Aware Design And Processed Data EDA Tool Interoperability


By Rajeev Jain, Kerim Kalafala, and Ramond Rodriguez Significant technology disruptions are on the horizon that will provide massive efficiency gains for EDA tool suppliers and semiconductor companies alike. These disruptions include the application of artificial intelligence and machine learning to enhance supplier tools and optimize user design flows and methodologies, and the ensuing migr... » read more

EDA In The Cloud


Hagai Arbel, CEO of Vtool, talks with Semiconductor Engineering about the benefits of moving EDA tools to the cloud, why it has been slow to take off, and what will drive this trend in the future. » read more

Primary, Anonymous, or What?


Top level primary I/Os remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications are multifold for RTL and gate level simulations of them. This paper studies the “simulation-impacting” features of design top IOs and the effect of each feature on v... » read more

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