CCIX Enables Machine Learning


It takes a lot of technology to enable something like machine learning, and not all of it is as glamorous as neural network architectures and algorithms. Several levels below that is the actual hardware on which these run, and that brings us into the even less sexy world of interfaces. One such interface, the Cache Coherent Interconnect for Accelerators (CCIX), pronounced C6, aims to make th... » read more

Improving VHDL


For the past several years, I have had the privilege to chair the IEEE 1076 VHDL working group. In March, we handed off the revisions to the VHDL LRM to our technical editor to finalize the document for balloting. As we are waiting for the standards process to finish up, I thought I would share my favorite new additions. Let me start with an executive summary: VHDL-2017 plus Open Source VHDL... » read more

Machine Learning Popularity Grows


Machine learning and deep learning are showing a sharp growth trajectory in many industries. Even the semiconductor industry, which generally has resisted this technology, is starting to changing its tune. Both [getkc id="305" kc_name="machine learning"] (ML) and deep learning (DL) have been successfully used for image recognition in autonomous driving, speech recognition in natural langua... » read more

The Future Of MEMS Design: Making MEMS Design More Like CMOS Design


MEMS-based component suppliers want to rapidly ramp their designs into high-volume production. This demand is driving MEMS suppliers to focus on ways to more efficiently re-use established process steps, stacks or technology platforms. To meet this need, we see the emergence of standard MEMS technology and design platforms similar to those used in CMOS design. The semiconductor industry and ... » read more

Dealing With System-Level Power


Analyzing and managing power at the system level is becoming more difficult and more important—and slow to catch on. There are several reasons for this. First, design automation tools have lagged behind an understanding of what needs to be done. Second, modeling languages and standards are still in flux, and what exists today is considered inadequate. And third, while system-level power ha... » read more

Transistor Aging Intensifies At 10/7nm And Below


Transistor aging and reliability are becoming much more troublesome for design teams at 10nm and below. Concepts like ‘infant mortality’ and 'bathtub curves' are not new to semiconductor design, but they largely dropped out of sight as methodologies and EDA tools improved. To get past infant mortality, a burn-in process would be done, particularly for memories. And for reliability, which... » read more

Is The IP Industry Healthy?


The semiconductor industry has been through many changes, each designed to reduce the total cost associated with the design and manufacture of chips. Twenty years ago, most companies had their own fabs and designed all of the circuitry on each chip. Today, only a handful of companies still own a fab and outsourcing design, in the form of intellectual property ([getkc id="43" kc_name="IP"]), has... » read more

Implementing High-Density-Advanced Packaging for OSATs And Foundries


HDAP design and verification require cooperation and collaboration between design houses, OSATs, foundries, and EDA vendors. By using common tools that have the integration and functionality needed to operate in both the IC and packaging domains and by developing and deploying process optimized design-kits such as ADK’s and PDKs, OSATs, foundries, and their customers can achieve design, fabri... » read more

EDA, IP Growth Hits Double Digits


The cloud, advanced packaging and AI/machine learning pushed up EDA and IP revenue to the highest Q1 growth level since 2011. Revenue was up 10.5% year over year to $2.168 billion, compared with $1.962 billion in Q1 2016, according to just-released numbers from the Electronic System Design (ESD) Alliance. The four-quarter moving average increased by 10.6%. The two largest regions, the Americ... » read more

EDA Moves Out Of The Shadows


EDA has long harbored ambitions that are larger than a piece of silicon. The engineering challenges being solved on a nanometric scale are remarkably similar to ones being solved at a much higher level—architectural design, layout, validation, verification, debug, thermal mapping, and a lot more. The problem, at least until recently, is that it has been difficult to gain a foothold in larg... » read more

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