Partitioning Becomes More Difficult


The divide-and-conquer approach that has been the backbone of verification for decades is becoming more difficult at advanced nodes. There are more interactions from different blocks and features, more power domains, more physical effects to track, and far more complex design rules to follow. This helps explain why the number of tools required on each design—simulation, prototyping, em... » read more

New Market Drivers


Semiconductor Engineering sat down to discuss changing market dynamics with Steve Mensor, vice president of marketing for [getentity id="22926" e_name="Achronix"]; Apurva Kalia, vice president of R&D in the System and Verification group of [getentity id="22032" e_name="Cadence"]; Mohammed Kassem, CTO for [getentity id="22910" comment="efabless"]; Matthew Ballance, product engineer and techn... » read more

Mashup At 7nm


The merger of two standards organizations typically falls well below the radar of most engineers, but folding the ESD Alliance (formerly known as the EDA Consortium) into SEMI is a different kind of deal. Ever since the introduction of finFETs and multiple patterning, EDA tools have become an integral part of the development of new manufacturing processes. Without those tools, there is no po... » read more

Tech Talk: Electrical Overstress


ANSYS Chief Technologist João Geada talks about electrical overstress and circuit aging and how what it means for automotive electronics. https://youtu.be/4bjdr0uvWG4 » read more

Applying Machine Learning To Chips


The race is on to figure out how to apply analytics, data mining and machine learning across a wide swath of market segments and applications, and nowhere is this more evident than in semiconductor design and manufacturing. The key with ML/DL/AI is understanding how devices react to real events and stimuli, and how future devices can be optimized. That requires sifting through an expandi... » read more

Looking At Test Differently


Wilhelm Radermacher, executive advisor at [getentity id="22816" e_name="Advantest"], sat down with Semiconductor Engineering to discuss how the impact of rapid market changes, advanced packaging approaches and increasing complexity on test strategies and equipment. What follows are excerpts of that conversation. SE: As we move into new markets where use models and stresses on devices are dif... » read more

Executive Insight: Wally Rhines


Wally Rhines, president and CEO of [getentity id="22017" e_name="Mentor, a Siemens Business"], sat down with Semiconductor Engineering to discuss a wide range of industry and technology changes and how that will play out over the next few years. What follows are excerpts of that conversation. SE: What will happen in the end markets? Rhines: The end markets are perhaps more exciting from a... » read more

Why EDA Needs To Change


Why is it taking so long for [getkc id="305" kc_name="machine learning"] to have an impact within EDA? Most of the time when I talk to the experts within the field I hear about why designs are so different from other machine learning applications, and I know that is true. Many of you reading this may not be aware that I was a developer of EDA tools for more than 35 years before I ended up writi... » read more

Regain Your Power With Machine Learning


It wasn’t too long ago that machine learning (ML) seemed like a fascinating research topic. However, in no time at all, it has made a swift transition from a world far-off to common presence in news, billboards, workplaces, and homes. The concept itself is not new but evidently what has caused it to take off is the rapid growth of data in many applications and more computational power. Closer... » read more

Achieving RTL-To-Netlist Equivalence


Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, there is a need to ensure flawless transformation of RTL code to the technology-dependent netlist. This in turns sets the requirements for the “design-for-implementation” coding, where designers ... » read more

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