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Blog Review: Aug. 4


Cadence's Paul McLellan listens in as industry luminaries celebrate 50 years of the microprocessor with a discussion on major challenges to the growth of microprocessors, inflection points over the last 50 years, and predictions for the next 25. Siemens EDA's Vladimir Kirichenko warns that designing electrical and thermal systems separately may lead to various problems such as late design ch... » read more

Startup Funding: July 2021


The trend of big funding for Chinese autonomous driving companies continued in July, with three startups each drawing $100M or more for efforts in ADAS and computer vision for automotive. The month also saw one electric vehicle manufacturer get a massive boost as it begins production on its first models, while significant funding also went to a company that wants to recycle used up EV batteries... » read more

Power/Performance Bits: Aug. 3


Efficient ADC Researchers at Brigham Young University, National Yang Ming Chiao Tung University, Texas Instruments, and University of California Los Angeles designed a new power-efficient high-speed analog-to-digital converter. The ADC consumes only 21 milli-Watts of power at 10GHz for ultra-wideband wireless communications, much lower than other ADCs that consume hundreds of milli-Watts to... » read more

Week In Review: Design, Low Power


Tools Vtool released a new version of its Cogita visual debug platform. New features aim to provide faster debug capabilities, including visual representation of test results using log files as input, improved manipulation and navigation throughout big logs, ML algorithms to classify data and find the relationship between inputs, and the ability to merge and compare test flow of two different ... » read more

Blog Review: July 28


Synopsys' Chris Clark considers potential vulnerabilities in automotive over-the-air updates and best practices and new standards the industry can implement to improve security of vehicle software updates. Cadence's Paul McLellan gets a look at expected new fab construction in the coming years and where capacity is being focused. Siemens' Robin Bornoff dives into electromagnetic simulatio... » read more

Power/Performance Bits: July 27


Amplifying light for lidar Engineers at University of Texas at Austin and University of Virginia developed a light detector that can amplify weak light signals and reduce noise to improve the accuracy of lidar. "Autonomous vehicles send out laser signals that bounce off objects to tell you how far away you are. Not much light comes back, so if your detector is putting out more noise than th... » read more

Week In Review: Design, Low Power


Tools Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL-to-signoff implementation flow. The tool aims to use reinforcement learning to find flow solutions that otherwise might not be explored and applies models to future designs. The company says it can improve productivity up to 10X and PPA up to 20% with optimization of the flow f... » read more

Blog Review: July 21


Cadence's Paul McLellan listens in as Partha Ranganathan of Google argues that a new era of Moore's Law is emerging, defined both by the efficient design of hardware accelerators and improving the ways that hardware is utilized. Siemens EDA's Chris Spear continues exploring classes in SystemVerilog with a look at the relationship between the class variables that point to an object and how to... » read more

Power/Performance Bits: July 20


Shrinking RFID chips Researchers at North Carolina State University built a new, tiny RFID chip. They expect the chip to help drive down costs for RFID tags, making it possible to embed them in more things for supply chain security. "As far as we can tell, it's the world's smallest Gen2-compatible RFID chip," said Paul Franzon, Professor of Electrical and Computer Engineering at NC State. I... » read more

Week In Review: Design, Low Power


Tools Andes Technology certified Imperas reference models for the complete range of Andes IP cores with the new RISC-V P SIMD/DSP extension. The reference models can be used to evaluate multicore design configuration options for SoC architecture exploration and support early software development before silicon prototypes are available. Cadence's digital full flow was optimized and certified... » read more

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