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Blog Review: March 24


Arm's Brian Cline points to a project with GlobalFoundries to demonstrate the feasibility and readiness of high-density, face-to-face, wafer-bonded 3D stacking technologies for high performance, energy-efficient designs. Synopsys' Taylor Armerding warns that while supply chain security risks aren't new, the recent SolarWinds breach should make everyone pay much more attention to dependencies... » read more

Power/Performance Bits: March 23


Metasurface for optical media Researchers at Purdue University proposed a new way to store information in optical media, such as CDs and DVDs, that could improve both storage capacity and read times. The development focuses on encoding information in the angular position of tiny antennas, allowing them to store more data per unit area. "The storage capacity greatly increases because it is o... » read more

Week In Review: Design, Low Power


Qualcomm finalized its acquisition of data center chip startup Nuvia with a price of $1.4 billion. Nuvia is working on a data center SoC and Arm-based CPU core it claims will lower performance per total cost of ownership by matching high performance with high efficiency and limiting maximum power to that which can be dissipated in an air-cooled environment. Qualcomm said Nuvia’s technology wo... » read more

Blog Review: March 17


Synopsys' Chris Clark considers the growing number of automotive sensors and the cost/performance tradeoffs between edge computing capability, sensor fusion, sensor degradation, monitoring, and the maintenance of the software over the lifespan of a vehicle. Cadence's Paul McLellan checks out how the process of loading the bootstrap into memory has changed over the years, from hand-entered on... » read more

Power/Performance Bits: March 16


Adaptable neural nets Neural networks go through two phases: training, when weights are set based on a dataset, and inference, when new information is assessed based on those weights. But researchers at MIT, Institute of Science and Technology Austria, and Vienna University of Technology propose a new type of neural network that can learn during inference and adjust its underlying equations to... » read more

Week In Review: Design, Low Power


Tools & IP Codasip unveiled three commercially licensed add-ons to the Western Digital SweRV Core EH1, aiming to allow it to be designed into a wider range of applications. The SweRV Core EH1 is a 32-bit, dual-issue, RISC-V ISA core with a 9-stage pipeline, open-sourced through CHIPS Alliance. The add-ons offer a floating-point unit (FPU) that supports the RISC-V single precision [F] and d... » read more

Blog Review: March 10


Siemens EDA's Harry Foster checks out how the maturity of verification processes impact bug escapes in FPGA designs and whether safety critical development processes prevent bugs from escaping to silicon. Synopsys' Dennis Kengo Oka examines the weaknesses and vulnerabilities in automotive keyless entry systems and how security researchers hacked the Tesla Model X key fob. Cadence's Paul M... » read more

Power/Performance Bits: March 8


Non-toxic, printable piezoelectric Researchers at RMIT University and University of New South Wales developed a flexible and printable piezoelectric material that could be used in self-powered electronics including wearables and implantables. "Until now, the best performing nano-thin piezoelectrics have been based on lead, a toxic material that is not suitable for biomedical use," said Dr N... » read more

Week In Review: Design, Low Power


Tools Synopsys introduced Euclide, a next-generation hardware description language (HDL)-aware integrated development environment (IDE). Euclide aims to enable earlier detection of bugs and optimize code for design and verification flows by identifying complex design and testbench compliance checks during SystemVerilog and UVM development. It assists correct-by-construction code development th... » read more

Blog Review: March 3


Siemens EDA's Ray Salemi considers incrementalism in engineering, the transition from drawing circuits to writing RTL, and the next big leap of using proxy-driven testbenches written in Python. Cadence's Shyam Sharma looks at key changes from LPDDR5 in the LPDDR5X SDRAM standard, which extends clock frequencies to include 937MHz and 1066MHz resulting in max data rates of 7500MT/s and 8533 MT... » read more

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