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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Research Bits: Oct. 29
By Jesse Allen - 29 Oct, 2024 - Comments: 0

Micro-LED DUV maskless lithography Researchers from the University of Science and Technology of China, Anhui GaN Semiconductor, and Wuhan University developed a vertically integrated micro-LED array for deep ultraviolet (DUV) maskless photolithography. The team fabricated a DUV display integrated chip with 564 pixels-per-inch density that uses a three-dimensional vertically integrated devic... » read more

Blog Review: Oct. 23
By Jesse Allen - 23 Oct, 2024 - Comments: 0

Cadence’s Sanjeet Kumar introduces the message bus interface in the PHY Interface for the PCIe, SATA, USB, DisplayPort, and USB4 Architectures (PIPE) specification, which provides a way to initiate and participate in non-latency-sensitive PIPE operations using a small number of wires. Siemens’ Dennis Brophy argues that the recently published Portable Test and Stimulus Standard (PSS) 3.0 ... » read more

Research Bits: Oct. 22
By Jesse Allen - 22 Oct, 2024 - Comments: 0

3D-printed active electronics Researchers from MIT demonstrated fully 3D-printed semiconductor-free resettable fuses. Produced using standard 3D printing hardware and an inexpensive, biodegradable polymer filament doped with copper nanoparticles, the device can perform the same switching functions as the semiconductor-based transistors used for processing operations in active electronics. A... » read more

Startup Funding: Q3 2024
By Jesse Allen - 16 Oct, 2024 - Comments: 0

Numerous new companies burst on the scene in the third quarter of 2024, including startups with plans for customizable RISC-V-based IP for applications from microcontrollers to data centers, high-speed data center interconnects, compute-in-memory LLM inference chips, and surveillance camera SoCs. Although it did not report funding, AheadComputing also launched last quarter to develop RISC-V cor... » read more

Blog Review: Sept. 25
By Jesse Allen - 25 Sep, 2024 - Comments: 0

Cadence’s Mamta Rana digs into how PCIe 6.1 ECN builds on the FLIT-based architecture introduced in PCIe 6.0, further optimizing flow control mechanisms to handle increased data rates and improved efficiency but making verification of shared credit updates essential. Siemens’ Nicolae Tusinschi provides a primer on formal verification, including what makes it different from simulation, pr... » read more

Research Bits: Sept. 24
By Jesse Allen - 24 Sep, 2024 - Comments: 0

Modeling negative capacitance Researchers from Lawrence Berkeley National Laboratory developed an open-source 3D simulation framework capable of modeling the atomistic origins of negative capacitance in ferroelectric thin films at the device level. When a material has negative capacitance, it can store a greater amount of electrical charge at lower voltages. The team believes the FerroX fra... » read more

Blog Review: Sept. 18
By Jesse Allen - 18 Sep, 2024 - Comments: 0

Siemens’ Kyle Fraunfelter explores the similarities between hurricane forecasting and semiconductor manufacturing to argue for the value of integrating real-time wafer fabrication measurements into the digital twin models used to simulate the semiconductor fabrication process. Cadence’s Rohini Kollipara introduces Display Stream Compression (DSC), which can enable higher resolutions and ... » read more

Research Bits: Sept. 17
By Jesse Allen - 17 Sep, 2024 - Comments: 0

DNA data storage plus compute Researchers from North Carolina State University and Johns Hopkins University created a DNA-based device that can perform both data storage and computing functions. “Specifically, we have created polymer structures that we call dendricolloids – they start at the microscale, but branch off from each other in a hierarchical way to create a network of nanoscal... » read more

Blog Review: Sept. 11
By Jesse Allen - 11 Sep, 2024 - Comments: 0

Cadence's Neha Joshi introduces the IEEE 1801 standard, also known as UPF (Unified Power Format), which offers a uniform framework for defining power domains, power states, and power intent to ensure consistency across diverse tools and phases of the design process. Siemens' John McMillan warns that known good die may not behave the same in 3D-ICs as they do standalone and suggests that mult... » read more

Research Bits: Sept. 9
By Jesse Allen - 09 Sep, 2024 - Comments: 0

All-silicon polarization multiplexer Researchers from the University of Adelaide and Osaka University propose an ultra-wideband integrated terahertz polarization (de)multiplexer implemented on a substrateless silicon base, which they tested in the sub-terahertz J-band (220-330 GHz) for 6G communications. “Our proposed polarization multiplexer will allow multiple data streams to be transmi... » read more

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