Author's Latest Posts


Blog Review: Mar. 27


Rambus' Steven Woo takes a look at the memory requirements of neural networks and why some companies are using on-chip memory while others are using HBM2 or GDDR6. Cadence's Lana Chan  observes growing momentum for NVMe and highlights some new features in the latest specification that are pushing mainstream adoption forward. Mentor's Matthew Ballance contends that when it comes to adopti... » read more

Power/Performance Bits: Mar. 26


Material holds both electrons, holes Researchers at Ohio State University discovered a material that can hold both electrons and holes. They hope the material, the layered metal crystal NaSn2As2, could simplify electronics, potentially removing the need for multiple layers or materials. "It is this dogma in science, that you have electrons or you have holes, but you don't have both. But our... » read more

Week In Review: Design, Low Power


Synopsys announced several new products: a new test family, a physical verification solution, and a software library for neural net SoCs. TestMAX, the new family of test products, includes soft error analysis and X-tolerant logic BIST for automotive test and functional safety requirements. TestMAX enables test through functional high-speed interfaces and supports early validation of DFT logi... » read more

Blog Review: Mar. 20


Cadence's Paul McLellan argues that rapid improvements in the performance of general-purpose computing led to a lack of innovation in domain-specific architectures, but as scaling slows, they're entering a new golden age. In a video, Mentor's Colin Walls takes a look at the use of floating point in an embedded application and some of the pitfalls associated with it. Synopsys' Taylor Armer... » read more

Power/Performance Bits: Mar. 19


Explainable AI Researchers from Technische Universität Berlin (TU Berlin), Fraunhofer Heinrich Hertz Institute (HHI), and Singapore University of Technology and Design (SUTD) propose a pair of algorithms to help determine how AI systems reach their conclusions. Explainable AI is an important step towards practical applications, argued Klaus-Robert Müller, Professor for Machine Learning at... » read more

Week In Review: Design, Low Power


M&A Nvidia will acquire Mellanox for $6.9 billion in cash, the largest deal in the chipmaker's history. Traditionally a PC GPU company, Nvidia has made a push into high-performance computing, particularly for AI workloads. Founded in 1999, Israel-based Mellanox focuses on end-to-end Ethernet and InfiniBand interconnect solutions and services for servers and storage. According to Nvidia, Me... » read more

Blog Review: Mar. 13


Mentor's Tom Fitzpatrick questions whether deep learning approaches can really help improve coverage in modern, complex designs. Cadence's Paul McLellan listens in at MWC as Huawei chairman Guo Ping defends the company's security practices and shows where its heading in 5G. Synopsys' Eric Huang checks out the newly announced USB4 specification, changes to previous USB names, and a few things ... » read more

Power/Performance Bits: Mar. 11


Reading qubits faster Researchers at Aalto University and VTT Technical Research Centre of Finland propose a faster way to read information from qubits, the building blocks of quantum computers. Currently, they are extremely sensitive to disruption even in cryogenic environments, holding quantum information for less than a millisecond. In the method now used to read information from a qubit... » read more

Week In Review: Design, Low Power


Cadence debuted Denali Gen2 IP for LPDDR5/4/4X in TSMC's 7nm FinFET process technology. The offering consists of PHY, controller and Verification IP. It supports both the pre-release LPDDR5 standard and LPDDR4/4X devices as well as Arm AMBA AXI buses and reliability features like in-line error correcting codes. The LPDDR5 standard provides up to 1.5x bandwidth over LPDDR4 and LPDDR4X. The US... » read more

Blog Review: Mar. 6


Synopsys' Snigdha Dua traces the evolution of memory from SDRAM to DDR5 and the techniques that provide each generation's speed increase. Cadence's Paul McLellan digs into the challenges of 112Gbps SerDes, including what makes PAM4 signaling different from NRZ and what goes into equalization and modeling. Mentor's Rich Edelman provides a quick tutorial on how to set up a custom UVM report... » read more

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