Analog: Avoid Or Embrace?


We live in an analog world, but digital processing has proven quicker, cheaper and easier. Moving digital data around is only possible while the physics of wires can be safely abstracted away enough to provide reliable communications. As soon as a signal passes off-chip, the analog domain reasserts control for modern systems. Each of those transitions requires a data converter. The usage ... » read more

Crossed Wires On Domains


Clock, power and reset domains can form a tangled web if systems are not architected correctly. Wires that cross these domains often require special treatment and additional analysis. They are all evolving independently, meaning that designers must keep up with the latest methodology guidelines and tool capabilities to ensure problems do not remain hidden until they get exposed in silicon. C... » read more

Designing In 4D


The chip design world is no longer flat or static, and increasingly it's no longer standardized. Until 16/14nm, most design engineers viewed the world in two dimensions. Circuits were laid out along x and y axes, and everything was packed in between those two borders. The biggest problems were that nothing printed as neatly as the blueprint suggested, and current leaked out of two-dimension... » read more

How FinFET Device Performance Is Affected By Epitaxial Process Variations


By Shih-Hao (Jacky) Huang and Yu De Chen As the need to scale transistors to ever-smaller sizes continues to press on technology designers, the impact of parasitic resistance and capacitance can approach or even outpace other aspects of transistor performance, such as fringing capacitance or source drain resistance. The total resistance in a device is comprised of two components: internal re... » read more

Challenges Grow For Finding Chip Defects


Several equipment makers are developing or ramping up a new class of wafer inspection systems that address the challenges in finding defects in advanced chips. At each node, the feature sizes of the chips are becoming smaller, while the defects are harder to find. Defects are unwanted deviations in chips, which impact yield and performance. The new inspection systems promise to address the c... » read more

Wrestling With High-Speed SerDes


SerDes has emerged as the primary solution in chips where there is a need for fast data movement and limited I/O, but this technology is becoming significantly more challenging to work with as speeds continue to rise to offset the massive increase in data. A Serializer/Deserializer is used to convert parallel data into serial data, allowing designers to speed up data communication without h... » read more

CEO Outlook: It Gets Much Harder From Here


Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

Verification At 7/5nm


Christen Decoin, senior director of business development at Synopsys, talks about what’s missing in verification, how is that affected by complex chips such as 7nm SoCs or AI chips, and why more steps need to be done concurrently. https://youtu.be/bz6KyJh67sI » read more

Selective Removal For Stronger Fins


By Matt Cogorno and Toshihiko Miyashita Remember when we could charge our mobile phones on a Sunday and not even think about it again until the next weekend? There was a time when battery life wasn’t even in the top ten concerns when purchasing a mobile phone. Today however, smartphones are constantly being used for computing, gaming, video streaming and other power-hungry applications, so... » read more

Realizing the Benefits of 14/16nm Technologies


The scaling benefits of Moore’s Law are challenging below 28nm. It is no longer a given that the cost per gate will go down at process nodes below 28nm, e.g., 20nm though 14nm and 7nm. Rising design and manufacturing costs are contributing factors to this trend. Meanwhile, the competing trend of fewer but more complex system-on-chip (SoC) designs is reducing the knowledge base of many chip... » read more

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