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Near-Threshold Computing Gets A Boost


Near-threshold computing has long been used for power-sensitive devices, but some surprising, unrelated advances are making it much easier to deploy. While near-threshold logic has been an essential technique for applications with the lowest power consumption, it always has been difficult to use. That is changing, and while it is unlikely to become a mainstream technique, it is certainly bec... » read more

New Materials Open Door To New Devices


Integrating 2D materials into conventional semiconductor manufacturing processes may be one of the more radical changes in the chip industry’s history. While there is pain and suffering associated with the introduction of any new materials in semiconductor manufacturing, transition metal dichalcogenides (TMDs) support a variety of new device concepts, including BEOL transistors and single-... » read more

Who Benefits From Chiplets, And When


Experts at the Table: Semiconductor Engineering sat down to discuss new packaging approaches and integration issues with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a... » read more

Highly Selective Etch Rolls Out For Next-Gen Chips


Several etch vendors are starting to ship next-generation selective etch tools, paving the way for new memory and logic devices. Applied Materials was the first vendor to ship a next-gen selective etch system, sometimes called highly-selective etch, in 2016. Now, Lam Research, TEL, and others are shipping tools with highly-selective etch capabilities, in preparation for futuristic devices su... » read more

HBM, Nanosheet FETs Drive X-ray Fab Use


Paul Ryan, vice president and general manager of Bruker’s X-ray Business, sat down with Semiconductor Engineering to discuss the movement of x-ray metrology into manufacturing to better control nanosheet film stacks and solder bump quality. SE: Where are you seeing the greatest growth right now, and what are the critical drivers for your technology from the application side? Ryan: One b... » read more

Next-Gen Transistors


Nanosheets, or more generally, gate-all-around FETs, mark the next big shift in transistor structures at the most advanced nodes. David Fried, vice president of computational products at Lam Research, talks with Semiconductor Engineering about the advantages of using these new transistor types, along with myriad challenges at future nodes, particularly in the area of metrology. » read more

Improving PPA In Complex Designs With AI


The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. Optimizing PPA involves a growing number of tradeoffs that can vary by application, by availability of IP and other components, as well as the familiarity of engineers with different tools and methodologies. Fo... » read more

End In Sight For Chip Shortages?


The current wave of semiconductor and IC packaging shortages is expected to extend well into 2022, but there are also signs that supply may finally catch up with demand. The same is true for manufacturing capacity, materials and equipment in both the semiconductor and packaging sectors. Nonetheless, after a period of shortages in all segments, the current school of thought is that chip suppl... » read more

Manufacturing Bits: Oct. 26


GaN finFETs, scaling GaN At the upcoming IEEE International Electron Devices Meeting (IEDM) in San Francisco, a slew of entities will present papers on the latest technologies in R&D. The event, to be held Dec. 11–15, involve papers on advanced packaging, CMOS image sensors, interconnects, transistors, power devices and other technologies. At IEDM, Intel will present a paper on a GaN-... » read more

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Performance


Profile variation is one of the most important problems during semiconductor device manufacturing and scaling. These variations can degrade both chip yield and device performance.  Virtual fabrication can be used to study profile variation in a very effective and economical manner and avoid process cycle time and wafer cost in the fab. In this short article, we will review the impact of STI (s... » read more

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