Foundries Prepare For Battle At 22nm


After introducing new 22nm processes over the last year or two, foundries are gearing up the technology for production—and preparing for a showdown. GlobalFoundries, Intel, TSMC and UMC are developing and/or expanding their efforts at 22nm amid signs this node could generate substantial business for applications like automotive, IoT and wireless. But foundry customers face some tough choic... » read more

System-Level Testing – The New Paradigm for Semiconductor Quality Control


Covering the history and trends of system-level test for semiconductors, this solution brief discusses: The increasing complexities of testing advanced semiconductor integrated devices across a span of applications: automotive, mobile computing, wearables, and more; Semiconductor trends driving necessary shifts in testing methodologies including SiP, SoC, 3D finFETs, heterogeneous compo... » read more

Building AI SoCs


Ron Lowman, strategic marketing manager at Synopsys, looks at where AI is being used and how to develop chips when the algorithms are in a state of almost constant change. That includes what moves to the edge versus the data center, how algorithms are being compressed, and what techniques are being used to speed up these chips and reduce power. https://youtu.be/d32jtdFwpcE    ... » read more

Power Issues Grow For Cloud Chips


Performance levels in traditional or hyperscale data centers are being limited by power and heat caused by an increasing number of processors, memory, disk and operating systems within servers. The problem is so complex and intertwined, though, that solving it requires a series of steps that hopefully add up to a significant reduction across a system. But at 7nm and below, predicting exactly... » read more

Thermal Impact On Reliability At 7/5nm


Haroon Chaudhri, director of RedHawk Analysis Fusion at Synopsys, talks about why thermal analysis is shifting left in the design cycle and why this is so critical at the most advanced process nodes. https://youtu.be/wjkrEFLb2vY » read more

A Paradigm Shift With Vertical Nanowire FETs For 5nm And Beyond


When I was in undergrad not so long ago, all my circuits and semiconductor textbooks/professors were talking about MOSFETs (metal-oxide semiconductor field-effect transistor) that were just “better” than BJTs (bi-polar junction transistor). There were still some old professors talking about how they did an excellent job using BJTs, but everyone knew it was MOSFET that was leading the game i... » read more

Advanced Defect Inspection Techniques For nFET And pFET Defectivity At 7nm Gate Poly Removal Process


By Ian Tolle, GlobalFoundries, and Michael Daino, KLA-Tencor During 7nm gate poly removal process, polysilicon is removed exposing both NFET and PFET fins in preparation for high-k gate oxide. If the polysilicon etch is too aggressive or the source and drain are not sufficiently protected, the etch can damage the active region and render the FET inoperative. Different materials are used in t... » read more

The Security Penalty


It's not clear if Meltdown, Spectre and Foreshadow caused actual security breaches, but they did prompt big processor vendors like Intel, Arm, AMD and IBM to fix these vulnerabilities before they were made public by Google's Project Zero. While all of this may make data center managers and consumers feel better in one respect, it has created a level of panic of a different sort. For decades,... » read more

Where FD-SOI Works Best (Part 2)


Semiconductor Engineering sat down to discuss changes in the FD-SOI world and what's behind them, with James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science; Giorgio Cesana, director of technical marketing at STMicroelectronics; Olivier Vatel, senior vice president and CTO at Screen Semiconductor Solutions; and Carlos Mazure, CTO at Soi... » read more

Who’s Paying For Auto Chip Test?


Testing of automotive chips is becoming more difficult and time-consuming, and the problem is only going to get worse. There is more to this than simply developing new test equipment or devising a better design for test flow. There are multiple issues at play here, and some of them are at odds with the others. First, no one has experience using advanced-node chips in extreme environments.... » read more

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