New Power Concerns At 10/7nm


As chip sizes and complexity continues to grow exponentially at 7nm and below, managing power is becoming much more difficult. There are a number of factors that come into play at advanced nodes, including more and different types of processors, more chip-package decisions, and more susceptibility to noise of all sorts due to thinner insulation layers and wires. The result is that engineers ... » read more

Noise Abatement


[getkc id="285" kc_name="Noise"] is a fact of life. Almost everything we do creates noise as a by-product and quite often what is a signal to one party is noise to another. Noise cannot be eliminated. It must be managed. But is noise becoming a larger issue in chips as the technology nodes get smaller and packaging becomes more complex? For some, the answer is a very strong yes, while for ot... » read more

Talking The Talk On Training


In my prior post, I discussed the value of good design flow training. A properly executed program can turn average engineers into above average problem solvers with the right tools and techniques. We got to thinking about this opportunity quite seriously at eSilicon. Is there a way to develop a focused, intense training program to create a new “army” of elite designers? In short, we thin... » read more

Tech Talk: 7nm Thermal Effects


ANSYS' Karthik Srinivasan talks about the effect of heat on reliability at advanced process nodes, including self-heating, circuit aging, and how that will affect automotive electronics. https://youtu.be/SS6iAXp0Kn8   Related Tech Talk: 7nm Power Dealing with thermal effects, electromigration and other issues at the most advanced nodes. » read more

Why Fabs Worry About Tool Parts


Achieving high yields with acceptable costs is becoming much more difficult as chipmakers migrate to next-generation 3D NAND and finFET devices—but not just because of rising complexity or lithography issues. To fabricate an advanced logic chip, for example, a wafer moves from one piece of equipment to another in what amounts to 1,000 process steps or more in a fab. Any glitch with the equ... » read more

How Reliable Are FinFETs?


Stringent safety requirements in the automotive and industrial sectors are forcing chipmakers to re-examine a number of factors that can impact reliability over the lifespan of a device. Many of these concerns are not new. Electrical overstress (EOS), electrostatic discharge (ESD) and [getkc id="160" kc_name="electromigration"] (EM) are well understood, and have been addressed by EDA tools f... » read more

Tech Talk: 7nm Litho


David Fried, chief technology officer at Coventor, digs into future scaling issues involving multi-patterning and new transistor types. https://youtu.be/FBnYRAL1xKY Related Stories Inside Next-Gen Transistors Coventor’s CTO looks at new types of transistors, the expanding number of challenges at future process nodes & the state of semiconductor development in China. Faster Time T... » read more

Transistor Aging Intensifies At 10/7nm And Below


Transistor aging and reliability are becoming much more troublesome for design teams at 10nm and below. Concepts like ‘infant mortality’ and 'bathtub curves' are not new to semiconductor design, but they largely dropped out of sight as methodologies and EDA tools improved. To get past infant mortality, a burn-in process would be done, particularly for memories. And for reliability, which... » read more

Inside FD-SOI And Scaling


Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation. SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI ... » read more

What’s Next In Scaling, Stacking


An Steegen, executive vice president of semiconductor technology and systems at [getentity id="22217" e_name="Imec"], sat down with Semiconductor Engineering to discuss IC scaling, chip stacking, packaging and other topics. Imec is an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies... » read more

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