Screening For Silent Data Errors


Engineers are beginning to understand the causes of silent data errors (SDEs) and the data center failures they cause, both of which can be reduced by increasing test coverage and boosting inspection on critical layers. Silent data errors are so named because if engineers don’t look for them, then they don’t know they exist. Unlike other kinds of faulty behaviors, these errors also can c... » read more

Radiation Tolerance Is Not Just For Rocket Scientists


As technology scales, soft errors from particle radiation are becoming increasingly concerning for in-field reliability. These radiation effects are called Single Event Upsets (SEU) and the frequency of the failures due to SEUs is known as the Soft Error Rate (SER). Soft errors are failures due to external sources. By contrast, hard errors refer to actual process manufacturing defects or electr... » read more

Which Foundry Is In The Lead? It Depends.


The multi-billion-dollar race for foundry leadership is becoming more convoluted and complex, making it difficult to determine which company is in the lead at any time because there are so many factors that need to be weighed. This largely is a reflection of changes in the customer base at the leading edge and the push toward domain-specific designs. In the past, companies like Apple, Google... » read more

Why Silent Data Errors Are So Hard To Find


Cloud service providers have traced the source of silent data errors to defects in CPUs — as many as 1,000 parts per million — which produce faulty results only occasionally and under certain micro-architectural conditions. That makes them extremely hard to find. Silent data errors (SDEs) are random defects produced in manufacturing, not a design bug or software error. Those defects gene... » read more

The High Price Of Smaller Features


The semiconductor industry’s push for higher numerical apertures is driven by the relationship between NA and critical dimension. As the NA goes up, the CD goes down: Where λ is the wavelength and k1 is a process coefficient. While 0.55 NA exposure systems will improve resolution, Larry Melvin, principal engineer at Synopsys, noted that smaller features always come with a process cos... » read more

Designing For Thermal


Heat has emerged as a major concern for semiconductors in every form factor, from digital watches to data centers, and it is becoming more of a problem at advanced nodes and in advanced packages where that heat is especially difficult to dissipate. Temperatures at the base of finFETs and GAA FETs can differ from those at the top of the transistor structures. They also can vary depending on h... » read more

Cryogenic CMOS Becomes Cool


Cryogenic CMOS is a technology on the cusp, promising higher performance and lower power with no change in fabrication technology. The question now is whether it becomes viable and mainstream. Technologies often appear to be just on the horizon, not quite making it, but never too far out of sight. That's usually because some issue plagues it, and the incentive is not big enough to solve the ... » read more

Near-Threshold Computing Gets A Boost


Near-threshold computing has long been used for power-sensitive devices, but some surprising, unrelated advances are making it much easier to deploy. While near-threshold logic has been an essential technique for applications with the lowest power consumption, it always has been difficult to use. That is changing, and while it is unlikely to become a mainstream technique, it is certainly bec... » read more

New Materials Open Door To New Devices


Integrating 2D materials into conventional semiconductor manufacturing processes may be one of the more radical changes in the chip industry’s history. While there is pain and suffering associated with the introduction of any new materials in semiconductor manufacturing, transition metal dichalcogenides (TMDs) support a variety of new device concepts, including BEOL transistors and single-... » read more

Who Benefits From Chiplets, And When


Experts at the Table: Semiconductor Engineering sat down to discuss new packaging approaches and integration issues with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a... » read more

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