Which Foundry Is In The Lead? It Depends.

More factors need to be weighed than just process scaling; leadership can vary month-to-month and by application.


The multi-billion-dollar race for foundry leadership is becoming more convoluted and complex, making it difficult to determine which company is in the lead at any time because there are so many factors that need to be weighed.

This largely is a reflection of changes in the customer base at the leading edge and the push toward domain-specific designs. In the past, companies like Apple, Google, Amazon, and Meta purchased the fastest commercially available processors. But over the past five years, these systems companies have been hiring teams of semiconductor hardware and software engineers to customize architectures for specific data types in order to greatly exceed the performance and power available through scaling.

That has not deterred TSMC, Samsung, and Intel from continuing to shrink features, and their roadmaps extend well into the 1.x nanometer range. But it has changed the dynamics of how they compete. Leadership is no longer just about the process geometry. Next-generation technology now includes everything from new types of transistors, interconnect materials and structures, and power delivery schemes. In some cases, flexibility may be required, whether that is hardware or software programmability, or simpler ways to create derivative designs in high-volume applications. In others, may be a matter of how many transistors can fit on a reticle-sized chip.

Process scaling remains important, despite rising costs and reduced power and performance benefits. Still, not every application requires it, and it is just one of a growing number of factors that determine market leadership. In fact, choosing which company is on top at any point in time may require a spreadsheet of offerings, rather than just a manufacturing process. And what’s important to one customer, or a particular design for that customer, may be very different from what’s important to another.

“There are lots of problems to solve, like how to design at the system level, how to partition everything and bring it all together,” said Kevin Zhang, senior vice president of business development at TSMC. “But these also represent an opportunity. The whole industry needs to figure out a way to do things better. We have to rethink system design in the future, and how to best partition these things. In the future you will see a system-level approach become more and more important, instead of at the individual chip level. This goes all the way from the software and software architecture down. You will probably see more and more significant players there becoming semiconductor customers.”

Eric Beyne, senior fellow and director of imec’s 3D system integration program, pointed to similar changes. “If you look at the edge, you want speed, low power, and a standard type of connection,” he said. “That’s do-able by most people. But then you have companies like AMD, Intel, Google, and so on, and they will want it a little better than the vanilla flavor from the shop next door. They want a tweaked version, or an interface that doesn’t need all the bells and whistles because they can do it differently.”

In AI training applications, for example, the goal is to cram as many compute elements as possible — often homogeneous — onto a piece of silicon. In a smart phone, in comparison, more logic is required for features such as image processing, but not all of it needs to be packed onto the same chip. And in applications such as AR/VR glasses, the heat limitations and performance requirements are so demanding, and variable by use case, that companies are experimenting with a variety of different architectures, from planar chips to 3D-IC architectures with complex thermal management.

Put simply, one size no longer fits all, and that is radically changing the dynamics of the foundry business. UMC and GlobalFoundries dropped out of the scaling race at 14nm (although GF has since moved to 12nm), focusing instead on a variety of specialty markets such as automotive and 5G. Since then, both have been running at full capacity and planning to add more, and they are expanding what can be done at mature nodes with the help of EDA and manufacturing equipment companies.

“The equipment suppliers are quite engaged,” said Gregg Bartlett, senior vice president of technology and research at GlobalFoundries. “Applied Materials created its ICAPS (IoT, Communications, Automotive, Power, and Sensors) business unit dedicated to things that are not single-digit nanometer-related technologies, whether it’s wide-band gap materials or compound semis or tooling capabilities that are relevant for CMOS image sensors. They need incredibly low metallics in the ion implanters. Advanced logic doesn’t care about that. So there are tool capabilities required that Moore’s Law scaling didn’t drop, and they have become new requirements. There’s an entire roadmap for what the other three-quarters of the market needs.”

Even at leading-edge nodes, processes are becoming different enough that it’s hard to compare. Some of that depends on the end market. Samsung and TSMC continue to battle it out on consumer electronics and PCs. Intel, meanwhile, continues to focus heavily on servers chips, often in competition with TSMC, but increasingly it is developing advanced-node chips for mil/aero applications, as well. And all of them stray into other markets, which continue to splinter as customers demand more bespoke solutions.

So each foundry is playing to its core markets, while expanding into others as budget and opportunities permit. Samsung is moving to gate-all-around FETs at 3nm, while TSMC and Intel plan to stick with finFETs at 3nm and move to GAA FETs at 2nm. And all of them are developing specialized processes at each of those nodes, along with a slew of half-nodes.

This is largely a reflection of the deep-pocketed needs of fabless systems companies, which are looking to maximize performance using the minimum amount of power. In this world, cost needs to be considered in the context of a system, or systems of systems. The economics of cooling fewer server racks that can do more processing in less space, and much more quickly, makes designing a chip from scratch at the most advanced nodes much more palatable. It’s a very different story for companies buying chips for a pre-defined socket.

As a result, Google’s server processing architecture looks very different than Tesla’s. And while each may contain 5nm or 3nm logic, they are customized for different data types, different memory and I/O configurations, and different priorities for how and where data is processed, how much needs to be kept, and where it is stored.

In this context, process technology and transistor type are still important, but they’re not necessarily the determining factors for what makes a chip run faster or use less power. In fact, getting to the most advanced nodes first with the next transistor technology is no longer a guaranteed winning formula. So while process leadership historically has been viewed in the context of density, increasingly that’s just one component in an increasingly heterogeneous collection of chips or chiplets in an advanced package. Just because a chip uses a 3nm process does not ensure it will run faster at lower power for a particular application than a 5nm logic chip, which may be packaged together with a neural processing unit, a CPU, and a GPU. Moreover, it may not perform as well over time if updates are required or algorithms change and there is no programmability built-in.

This is evident in the the roadmaps for the different foundries. While there are some similarities, there also are distinct differences, and those differences are likely to widen over time.

Samsung Foundry is expected to introduce its SF3E (3nm) process technology later this year or next, based on a gate-all-around transistor it calls MBCFET, with a 23% speed improvement using 45% less power. Samsung will be first to market with GAA FETs, which control current leakage better than finFETs at the most advanced nodes — basically being able to turn transistors completely off rather than watching batteries slowly drain even when they’re turned off. The company also will add its SF4E, 4, 4P for the mobile market. The 4P, which is expected sometime next year, will offer 1.19X performance increase using a 4nm process with new middle-of-line technology.

SF3 and SF3P will be introduced next year, with SF2 expected to debut in 2024, followed by SF1.4 sometime in the 2026-2027 timeframe.

In addition, Samsung will beef up its packaging options with its Cube S, a 2.5D version based on a hybrid silicon interposer, along with hybrid BGA and TCP BGA versions. Its 3D-IC X-Cube, which will be available in 2024 using microbumps, will be followed two years later with a bumpless version, presumably using hybrid bonding or some other high-speed, low-resistance material used to join them.

Fig. 1: High-speed, low-resistivity interconnects and shorter distances can dramatically improve performance and reduce both power and heat. Source: Samsung

One of the biggest concerns at the most advanced nodes is heat. GAA FETs will help somewhat with that, but increased utilization of chips and higher dynamic power density can trap heat between vertical structures. In general, there are two ways to deal with that. One involves physically cooling it, using a heat sink or some form of thermal transference into liquid, or internally using microfluidics. The second is to reduce the threshold voltage of the individual parts.

“If you can reduce the power consumption with a lower threshold voltage, you can decrease the power dissipation that is limiting so much performance,” said Indong Kim, vice president of product planning at Samsung Electronics.

One associated challenge is that memory requires a minimum voltage to function properly, so voltage needs to be stepped up and down to make this work. Samsung has the benefit of making its own memory — DRAM (including HBM), NAND, SRAM, STT-MRAM — so it has the ability to experiment with this in-house. It even has developed in-memory compute capabilities. This is important because lowering the voltage can increase susceptibility to a variety of types of noise, and all of that needs to be considered when building advanced chips. Jim Elliott, executive vice president of memory sales at Samsung, said that by using finFETs in DRAM, the power can be scaled to less than 0.9 volts.

Samsung also is developing various bridge technologies, including an embedded bridge, and what it calls an “RDL interposer.” In 2025, the company also expects to add backside power delivery, which will help relieve the congestion inside the chip. What makes this approach appealing is the combination of reduced congestion in an extremely dense sea of 3D transistor structures, and the focus on doing more in the redistribution layer, which has largely been looked at as a mechanical foundation in the past.

Samsung likely will use many of the chips it develops internally in its various product lines, which now includes automotive, mobile/consumer, IoT, and HPC/AI. “This is a foundry total-design platform,” said Moonsoo Kang, executive vice president at Samsung.

Despite the reduced leakage offered by GAA FETs, TSMC sees enough benefit at what it calls N3 to delay the introduction of that technology until N2. Yuh Jier Mii, senior vice president of R&D, said N3 will provide an 18% performance improvement at the same power as N5, or a 34% power reduction at the same performance. At N2, when nanosheets are introduced, there will be about a 10% to 15% performance increase, or a 25% to 30% power reduction.

Mii also pointed to a follow-on technology to nanosheets, a complementary FET, which is the likely path all three of the major foundries will take. What isn’t clear yet is when exactly that will happen, or whether there will be an interim technology developed by imec, called a forksheet FET.

TSMC has been experimenting with novel materials and transistors, including carbon nanotube FETs, which will offer scaling density of 1.5X to 2X over other transistor types, Mii said. New low-resistance materials could reduce resistance by 40%, which would significantly increase performance, reduce the amount of power needed to drive signals, and significantly reduce heat. “Less resistivity has the potential for further scaling with enhanced interconnect performance,” he said.

On the packaging front, TSMC already has been in high-volume manufacturing with its Integrated Fan-Out (InFO) technology, and it is working with customers on 3D-ICs based on its chip-on-wafer-on-substrate (CoWoS) technology using microbumps, as well as organic and silicon interposers.

The company also has developed a high-density silicon bridge, and it is developing a front-end-of-line packaging technology called system-on-integrated-chips (SoIC), which utilizes horizontal and vertical space to embed chiplets into a die.

Like TSMC, Intel will push finFETs one more node, with plans to swap over to nanosheets at 2nm, or what it calls 20A (20 angstroms equals 2nm) — in 2024. Intel’s GAA FET is called a RibbonFET. It also plans to add backside power delivery, what it calls PowerVia, at 18A in 2025.

While Intel plans to achieve parity or leadership on advanced process nodes, the company’s push into chiplets and its experience with developing chiplets, and bridging them together using its Embedded Multi-die Interconnect Bridge (EMIB) technology are noteworthy. The company also has created die-to-die stacking technology called Foveros, which is the 3D version of EMIB.

Intel essentially has created a chassis for customizing devices for customers, able to swap different components in and out, depending upon customer needs, and its purchase of Altera back in 2015 provides needed flexibility to extend the life of these heterogeneous solutions as algorithms and protocols change. Its decision to buy Tower Semiconductor earlier this year adds a suite of specialty and mature-node capabilities that can be bundled into those packages.

And the company has invested heavily in foundry services to help customers develop customized solutions.

“For internal manufacturing, we are really trying to get back into process technology leadership, and we will do multiple nodes in the next four years,” said Rahul Goyal, vice president and general manager of product and design ecosystem enablement at Intel. “Second is external manufacturing. We are a product company, so we are going to utilize whatever is optimal for a product line and for that product to be manufactured. So as an external foundry, we will make that happen. And we are doing a lot more on the leading edge, as well. We also are building our foundry from the ground up. The last incarnation was Intel Custom Foundry. This time we deliberately are called Intel Foundry Services, because we are a services business.”

Intel also is getting some help from the U.S. government by way of the CHIPS Act, which is enabling it to build fabs and an educated workforce in places like Ohio, and it has struck a deal with the U.S. Military, Aerospace and Government (USMAG) alliance to enable chip design and production at the most advanced process technologies. Intel is the only leading-edge U.S.-based foundry of the big three, and it stands to benefit from geopolitical strife and government investment.

Despite all of this very expensive advanced manufacturing and packaging technology, concerns about reliability are rising. It now depends on a spreadsheet of variables, from manufacturing defects that can produce silent data errors to thermal hot spots.

“In the past, people thought heat would spread from these hot areas to cold areas so that you would get an even distribution of power on your chip, and then you could cool it evenly from the outside,” said imec’s Beyne. “Unfortunately, if you wait until the heat spreads, the temperature is already too high. So you have to increase the cooling, and with the increase in cooling you localize these hot spots. And the neighboring silicon doesn’t help you at all. It has to go vertical. So you have to go to more direct cooling solutions.”

Manufacturing processes are now huge material science challenges. Some materials need to dissolve or melt away, while others need to remain intact, and all of this needs to happen during the same process step in order to ensure sufficient throughput in the fab.

“This is big enough where we had to create new programs associated with cleaning and defectivity testing,” said Kim Arnold, chief development officer at Brewer Science. “The materials need to be able to withstand really high temperature stabilities of 400°C and higher. Once you get it to survive something like that, or harsh chemicals, some of these are even more difficult to remove in a reasonable manner. This has spawned other program activities we never really anticipated a few years ago.”

To put this in perspective, what used to be a fairly straightforward metric — who could migrate to the next process node fastest — has become a convoluted and much larger set of metrics that may be very different from one application to another.  In some cases, it may be as simple a question of which foundry has enough capacity at any point in time to hit a market window, while in others it may involve a complex set of tasks and combinations of materials for which there is no precedent. And just because one foundry introduces a 3nm or 2nm process, doesn’t mean it’s the same as another’s.

While scaling remains important, it may apply only to one or more small logic chips included in an advanced package, where the real advantage is the expertise required to integrate all of the various pieces, or the design of the package itself. Which foundry can build the best disaggregated SoC for a specific application or use case is becoming much harder to determine when the individual pieces don’t line up, but all the top-line boxes are checked. Performance and power are becoming application-dependent attributes, and sometimes as narrowly defined as a specific configuration for a single customer.

Scaling Roadmaps

Fig. 2: Samsung

Fig. 3: TSMC

Fig. 4: Intel

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DylanP says:

Nice article Ed. I do agree that we are in a unique situation where each one of the big 3 has a shot at pulling ahead, something that we havent seen for quite a few years.

However while they all have a chance, it definitely isnt an equal one.

Samsung likes to compare their ‘3nm’ GAP to their 5nm nodes, not to their improved 4nm, making the jump look much bigger than it actually is. They also said they were delivering 3nm GAP 6 months ago. For all intents and purposes, 3nm GAE is delayed at Samsung.

Intel is the real challenger here. With new leadership, accelerated roadmap and a focus back on engineering and fabs, Intel is seemingly heading back to their glory days. They’ve had issues in the past executing on time, but with Intel 7 shipping in mass volume for the last year, and Intel 4 already in production, they have seemingly set themselves back on track. Getting into EUV and being the first to utilize ASML’s latest and greatest High-NA EUV machines, will likely accelerate their roadmap and density gains.

TSMC is the reigning champ, and the biggest in the industry, but for the first time in a long time they are having trouble. TSMC’s 3nm is late, it was originally supposed to ship this year to Apple, but has been pushed into 2023, and Apple has had to do third year of N5/N4, which they are not happy with, and the lackluster gains in both the M2 and A15 chips. TSMC facing delays while Intel isnt has really closed the gap between these two fabs and we will likely see it shrink narrower and narrower each year until Intel matches or surpasses them in 2024/2025.

Volume wise you can always bet on TSMC, but they might not be the node leader for much longer.

Also with China proclaiming it will reunify (go to war) with Taiwan in the upcoming years, even if there isn’t a shakeup based on technology, that war would decimate TSMC and turn the leading edge nodes into a duopoly of Intel and Samsung. It’s a very real and big concern — hence, why the U.S and EU are pumping money into Intel for them to create more domestic fabs.

Dr. Dev Gupta says:

For the Chiplet concept ( a rehash of IBM MCMs circa late ’70s ) to fly, Adv. Packaging ( AP ) has to keep reducing the Parasitics of Package level Interconnects and at the same time increase the areal Density of Bandwidth. So far as AP goes 2-d, 2.5d have pretty much reached the limits. In these Packages ( say using EMIB, sinc last Spring inFO – LSI etc ) now the inter die Interconnect length is NO LONGER decided by the distance between dies as in earlier Packages / Modules BUT by the size of dies assembled on a plane ( as in the Apple M1 Ultra with two rather huge 24 mm long dies Packaged with inFO – LSI ) ! So 3-d stacking of chiplets using the finest pitch Flip Chip ( e,g. HBC at 9 um ) is the obvious alternative but things can get more complicated than in a HBM w/ 8 die stack ( using u Pillar Flip Chip at a pitch of 50 um ) of equal sized DRAMs when chiplets with irregular sizes / shapes need to get stacked, at times w/ HOT Processors in the middle of the stack. IMEC’s Eric states the obvious, but heat extraction from these interior dies must n’t add too much to the interconnect length, bulk, yield, reliability and of course cost. For a “beyond the obvious” and in depth discussion of the technologies needed to fill these gaps in 3-d stacking, look up the IEEE IRDS Roadmap for Semiconductor Devices for guidance ( NO obscure Greek names either ! ) by people in the US who actually predicted and developed the latest AP technologies now in use worldwide.

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