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Big Changes In Architectures, Transistors, Materials

Who’s doing what in next-gen chips, and when they expect to do it.

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Chipmakers are gearing up for fundamental changes in architectures, materials, and basic structures like transistors and interconnects. The net result will be more process steps, increased complexity for each of those steps, and rising costs across the board.

At the leading-edge, finFETs will run out of steam somewhere after the 3nm (30 angstrom) node. The three foundries still working at those nodes — TSMC, Samsung, and Intel, as well as industry research house imec — are looking to some form of gate-all-around transistors as the next transistor structure in order to gain tighter control over gate leakage.

This approach is likely to work for at least a couple more nodes after that, and possibly further with the rollout of forksheet FETs, an intermediary step developed by imec. (See figure 1) Yet each of these companies is using different naming conventions, timelines, and technology mixes, making it difficult to determine which has technology leadership at any particular moment.

Fig. 1: N and P-type forksheet FET pair (left) and stacked nanosheet FET (right). Source: imec

Fig. 1: N and P-type forksheet FET pair (left) and stacked nanosheet FET (right). Source: imec

“If you look back, we started with bipolar devices, and then we moved to planar CMOS and to 3D finFETs,” said Kevin Zhang, senior vice president of business development at TSMC. “Now we’re moving to nanosheet gate-all-around transistors. But the transistor structure is going to evolve. It’s not going to be every generation or node, where you have to bring in a new architecture, because new transistors or architectures take a long, long time. We have been investing in nanosheet technology for over 10 years in order to have enough confidence to introduce it at the 2nm node.”

Foundries will extend existing technologies as long as possible, because each change is costly. In addition to new manufacturing processes developed by the foundry, it requires fine-tuning hundreds of process steps involving manufacturing equipment. The key metrics here are time spent in manufacturing for each wafer, which contributes to cost, and time to adequate yield. Each step requires changes in everything from EDA tools, which need to be certified at each node and half-node for each foundry, to exactly when various equipment is inserted into the manufacturing flow. There can be multiple insertion points for complex chips. That makes actual timelines hard to pin down, and foundries may not push to the next technology node until they run out of improvements using existing technology.

TSMC, the current process leader — and the only pure-play foundry at the leading edge — plans to migrate to GAA FETs at 2nm. Yuh-jier Mii, senior vice president of R&D at TSMC, said in a recent presentation that finFETs at 3nm will offer 18% speed improvement using the same power, or 34% power reduction at the same performance. With nanosheets, there will be about a 10% to 15% speed improvement, a 25% to 30% power reduction, and 1.1X density increase. He also noted that existing design rules will be compatible at N2, which will allow reuse of IP.

Intel will follow a similar path, using its version of a GAA FET, called a RibbonFET. Intel likewise has said it has enough improvements left in its finFET technology to extend finFETs for one more node.

“We are offering an advanced finFET at the current production node,” said Rahul Goyal, vice president and general manager of product and design ecosystem enablement at Intel. “We also are looking at the next-generation node, which will be coming out in the next year or so. And then our sweet spot — which is the most advanced node and where we believe we can have differentiation — is in development with several customers. This gets us into the 2024 to 2025 time frame, and a better understanding of what our customers need and how to make it happen. The challenge is making sure we are working with our customers in the early phase to accelerate our learning as much as possible, and then also to enable our ecosystem and partners to serve our customers. The ecosystem is very powerful, and has become extremely vibrant over the years. There’s a lot of R&D in that ecosystem.”

Samsung, meanwhile, will introduce GAA technology at 3nm, which it calls Multi-Bridge Channel FETs. The company claims this technology can reduce power consumption by 45%, improve performance by 23%, and reduce area by 16% versus a 5nm finFET. The following generation will reduce power consumption by up to 50% and improve performance by 30%, using 35% less area. One of the key improvements Samsung is touting is adjustable channel widths, which can reduce the power needed to drive signals.

What’s next?
After GAA FETs, the next rev of technology likely will include stacked GAA FETs, also known as complementary FETs (CFETs), for up to 50% scaling. This change extends nanosheets a couple more nodes, at least. How many layers can be stacked up may determine the extensibility of this technology.

“We’re looking at lateral nanowires, nanosheets, and some degree of stacking of lateral nanowires and nanosheets for the next few technology generations,” said David Fried, vice president of computational products at Lam Research. “Everybody likes to survey the full list of advanced devices and look at vertical and lateral devices and stacks, but the investment required to make any of these changes is so significant that manufacturers had better be certain that they are going to get at least a few nodes out of a major transition before they make that transition. You try not to make these decisions one node at a time.”

CFETs are expected to start showing up somewhere around 14 angstroms (1.4nm), or whatever the actual number is — at this point, it has not been determined. CFETs have been on the drawing board for more than a decade, and are considered an evolutionary step from nanosheet and forksheet FETs. With CFETs, nFET and pFET wires are stacked in one- or two-wire configurations, providing an area and density benefit while still limiting current leakage at the gate. That leakage is why a battery drains or electricity continues to flow even when a device is turned off.

Fig. 2: CFET architecture. Source: Coventor, a Lam Research Company

Fig. 2: CFET architecture. Source: Coventor, a Lam Research Company

Rethinking some basics
Unlike in the past, when a process could be ironed out over billions of units of the same design, end users are demanding more customized solutions for a particular application. In some cases, these are being designed for internal consumption, such as a hyperscale data center. That limits the amount of industry learning to a specific design, which is further reduced by smaller volumes.

To make matters worse, some of these devices are being used in safety- and mission-critical applications. So in addition to being produced in limited numbers, there is demand for increased reliability over longer lifetime.

In response, a number of interesting strategies are under development to deal with these and related issues. For example, rather than expecting every transistor or interconnect in a design to work perfectly — at 100% yield — the idea is to be able to identify which ones are bad, or go bad, at any point in a chip’s lifetime. The emphasis here is on resilience. In the past, this was accomplished with redundancy, and the general attitude was that transistors are free. But that approach is too expensive in a heterogeneous design, where some of the compute elements and memories are created by the different vendors.

“There are two issues,” said Andrzej Strojwas, CTO of PDF Solutions. “First, how do you determine very early that a circuit is not going to work? And second, how do you build a reconfigurable interconnect? You can use active circuitry to reconfigure that interconnect. The standard way of doing this is you do the testing after the fabrication process is over and you burn the fuses. But if you have the information inline, via eBeam scanning at the low-level metal levels, you can do this much more efficiently. The granularity is different.”

When Sony introduced the Playstation 2 in 2000 based on IBM’s Cell processor, it was designed with six cores even though only five were needed. The approach was considered revolutionary at the time. But reconfigurability adds a whole new level of understanding about what’s happening from design through manufacturing, including real-time analytics, the ability to reroute signals as needed, and to partition designs with much more precision.

Lithography is about to undergo a significant and costly shift, as well. EUV, deployed for high-volume manufacturing at 5nm after about a decade of delays, already is falling behind. At 3nm and 2nm, multi-patterning again will be needed unless ASML — the only source for leading-edge lithography equipment — can roll out high-numerical aperture EUV (high-NA EUV), and at a price point that makes sense. High-NA EUV has an aperture of 0.55, versus 0.33 for EUV, and it uses an anamorphic lens to be able to correctly print features at the edges of a wafer. But not all metal layers will require high-NA EUV, which means it likely will be integrated into the manufacturing flow as a point tool rather than one-size-fits-all.

Another strategy that is gaining traction is design technology co-optimization, which links front-end design with manufacturing much more closely than in the past. DTCO has been around for years, but it has only gained use at the most advanced nodes.

“In the planar CMOS era, designers and technologists could predict how a node would scale,” said Ricardo Borges, product marketing director in Synopsys’ Custom Design and Manufacturing Group. “That kind of intuition became less credible with the introduction of finFETs, which introduced some new things into the mix and made predicting the characteristics of the node more difficult. Today, there is more variety and a greater number of architectures that need to be explored. For example, in the near-term, we are seeing early releases of gate-all-around technologies. Beyond those, there are other types of GAA architectures and more materials that need to be evaluated. At some point, there could be a replacement for silicon with other materials. We’re already seeing novel metals like ruthenium and molybdenum being considered as alternatives to copper because they offer lower resistivity. And then there are certain constructs, which imec calls scaling boosters, that might be a new process technique to reduce the variability of a patterning approach.”

Yet another approach is simply not to scale to the most advanced nodes at all. Foundries such as UMC and GlobalFoundries are investing heavily at mature nodes, where alternative approaches are being used to boost PPA. Gregg Bartlett, senior vice president of technology, engineering and quality at GlobalFoundries, said 80% of the chips in use today are manufactured at mature nodes, and he expects that number to increase with growth in advanced packaging, hybrid bonding, chiplets, and more domain-specific designs.

That doesn’t make designs at mature nodes any less complex, though. “We start with materials and then design the chip, rather than starting with the end market and figuring out what they want to do with the design and what materials map into it,” Bartlett said. “SOITEC has 27 different kinds of SOI (silicon on insulator) materials with different thicknesses of the box, different thicknesses of silicon, and different crystal orientations. Understanding why one substrate is better than another is a really important consideration. And it’s not because of the material properties. It’s because by the time it’s integrated all the way into performance at the system level you understand how this translates.”

Different options
What’s surprising is just how much R&D is happening at all process nodes, not just at the leading edge, and that research is likely to explode with the passage of the CHIPS And Science Act in the United States and the European Chips Act, which will funnel collectively more than $100 billion in to research of a variety of related fields.

This includes silicon photonics for multi-chip and multi-module/package communication, which has been used extensively inside of data centers to connect servers to storage. Increasingly, it will be used over shorter and shorter distances. Light is very fast, takes minimal energy to actually transmit signals, and it generates very little heat. But it also requires monitoring for thermal fluctuations, which can push signals outside the range of filters, and inspection for any roughness in waveguides, which affects signals. Unlike electrons, photons don’t like corners, which is one of the challenges in building photonics into chips.

“For us, we want to be able to simulate two devices bottled together in some shape or fashion, and to be able to emulate and simulate a combination of both of those,” said Bartlett. “The EDA guys are doing a good job of keeping up in the background. We just had an announcement with one of the EDA suppliers on our 45CLO platform (C, L, and O are different wavelength bands, each with different loss) because now you’re trying to do electro-optics. Those are areas that are at the forefront of the industry, and we’re trying to enable our customers with the right design tools.”

Specialty foundry offerings are booming, as well. “Strong wafer demand kept our fabs operating at full capacity, and higher-than average blended pricing with our overall revenue,” said UMC President Jason Wang, during a recent earnings call. “SoC technologies, such as non-volatile memory, power management, RF-SOI, and OLED display drivers are necessary applications across 5G, AIoT, and automotive. And our strategy to focus on specialty technologies has been successful — it now contributes more than half of our wafer revenue.”

Wang noted that the continued electrification of automobiles is a catalyst for future growth, as well.

Other options
Perhaps the biggest shift of all comes in the way of packaging options and chiplets. There are many ways to put different pieces together, including a mix of digital logic developed at the most advanced nodes with other logic, analog, and various types of memories developed at mature nodes. In fact, as designs become increasingly heterogeneous and customized for specific applications and use cases, there is a growing need to add even greater flexibility into them.

“One customer we talked to had a very complex interrupt controller,” said Andy Jaros, vice president sales, marketing and solutions architecture at Flex Logix. “They needed to anticipate all the different permutations their customers would want to boot up their chip, including which peripherals to connect or make available to the external world, and they were trying to do that under software control. What they found is that no matter how they configured it or how complex that interrupt controller was, that interrupt controller wouldn’t be supported. That’s where the embedded FPGA comes into play. You can have a much simpler interrupt controller, and that interrupt controller is targeted and specifically designed for each customer. So now you don’t have to anticipate every potential boot case or boot sequence or combinatorial variation. Basically, when the customer needs it, you generate some new RTL and drop it in for that customer’s sequencing requirements.”

Mixing and matching various components and processes produces some unexpected results, as well. Consider hybrid bonding, which provides a much more direct way of connecting different components than soldering them together.

“Because of solder’s slow temperature processes, it restricts a lot of the downstream applications they want to do,” said Kim Yess, executive director of the Wafer Level Processing Business Division at Brewer Science. “We’re also seeing where customers were doing solder ball integration that they’re having so much deformation or fracturing that they’re now considering hybrid bonding. It’s going to be quicker than true heterogeneous integration.”

Copper-to-copper hybrid bonding is the farthest along, but there is work underway to use dielectrics for the bond. “We’re working in parallel with a polymeric dielectric to do the same thing,” said Dongshun Bai, a scientist at Brewer Science. “It’s still in the early development stage.”

Another advantage of hybrid bonding is that it reduces the stress points in bonding, which can cause cracks in the solder balls, particularly at the corners. “We’ve heard about major challenges such as lateral alignment,” said Bai. “If the alignment is less than 2 microns, they may have some issues. And if the microbump connection becomes smaller, stability will be a concern.”

The future
Unlike in the past, when the whole chip industry was marching in lock step to the next process node, there are many possible avenues under consideration. There is work at existing nodes to more accurately print features on wafers using curvilinear mask shapes. “Today if you want to draw a certain shape on the wafer reliably, we manipulate the shapes on the photomask pretty aggressively,” said Aki Fujimura, CEO of D2S. “Often the shape on the mask ends up looking nothing like the intended shape on the wafer.”

This is where curvilinear masks fit in. “It’s getting harder and harder every technology node, even with EUV, to get the wafer shapes to be as uniform as possible across manufacturing variation,” Fujimura said. “It’s been well established for about two decades that the best uniformity is achieved by using curvilinear shapes on mask. This is where multi-beam mask writers come in. Now that the majority of the leading edge masks are written with multibeam mask writers, curvilinear shapes are possible to manufacture. In the prior generation with variable-shaped beam (VSB) technology, curvilinear mask shapes were impractical to write.”

And if that’s not sufficient, there are development efforts underway involving 2D materials for carbon nanotube FETs, which are on the radar of all the leading foundries. Whether those structures actually will materialize for mainstream applications, for specialty chips, or at all remains to be seen. While research into different transistor structures using exotic materials continues,  leading foundries are looking toward architectures and advanced packaging as possible paths forward, either with or without the help of OSATs.

What appears certain is that competition is heating up rather than subsiding, and the race is on to “mass customize” semiconductors quickly, at the lowest cost possible, and with maximum reliability. The question now is which is the best path forward, and that remains to be proven.

Related
Scaling, Advanced Packaging, Or Both
Number of options is growing, but so is the list of tradeoffs.
Hybrid Bonding Moves Into The Fast Lane
Companies are speeding ahead to identify the most production-worthy processes for 3D chip stacking.
New Materials Open Door To New Devices
2D materials add process challenges, but deliver significant performance benefits.
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