Mask Economics Shape High-NA EUV Adoption


Key Takeaways: Mask costs are not stopping leading-edge scaling, but they increasingly influence design, node, and process choices. High-NA EUV will tighten requirements for CD, EPE, local CDU, mask 3D modeling, stitching, and materials. Reduced depth of focus in High-NA EUV will drive new resist, etch, film, and absorber approaches. Experts at the table: Semiconductor Engin... » read more

Chip Industry Week In Review


Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

Curvilinear Masks Push The Limits Of Inspection And Metrology


Key Takeaways: Curvilinear masks require native data flows across design, mask data prep, writing, inspection, and metrology. Inspection is shifting from finding all defects to identifying which mask variations actually print on wafer. High-NA EUV will intensify inspection challenges, particularly for small printable defects and actinic contrast limits. Experts at the table... » read more

Enabling Production-Ready AI For Semiconductor Manufacturing


Semiconductor inspection has always been a scalability problem. Inspection teams are buried in manual reviews because the machines on the line throw false rejects, miss real defects, and can't learn from the data they're already producing. The job hasn't really changed in decades. Find defects faster. Find them with higher sensitivity. Keep cost down. And whatever you do, don't bury the review ... » read more

Mask Technology Faces A New Set Of Challenges


Key Takeaways: Mask inspection and repair remain the critical bottleneck, even as multi-beam writers have reduced mask-writing constraints. Curvilinear masks are becoming viable for critical layers, but qualification, metrology, and inspection standards still lag production needs. Scaling curvilinear requires curvilinear-native data flows, model-based checks, GPU/HPC compute, and les... » read more

Chip Industry Week In Review


Acquisitions and business pivots Teradyne acquired Israel-based TestInsight, a semiconductor test provider with pattern conversion, validation, and virtual test capabilities. Credo plans to acquire DustPhotonics, a developer of silicon photonics PICs for optical transceivers. Molex plans to acquire Teramount, a provider of detachable, passive-alignment fiber-to-chip connectivity solu... » read more

eBeam Initiative At SPIE ALP 2026: Continuing Progress On Curvilinear, EUV, And Data Challenges


The eBeam Initiative’s annual lunch at SPIE Advanced Lithography and Patterning has long served as a focal point for eBeam technology education for the industry. This year marked our 17th gathering, with approximately 150 attendees joining us. As in past years, the value of the session was less about any single topic and more about the collective signal across different parts of the ecosystem... » read more

Challenges In Scaling Chips To 2nm And Below


Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

Chip Industry Week In Review


Big Deals and Fundings Rapidus secured US$1.7B in a new funding round from the Japanese government and the private sector to ramp 2nm production by next year. Open AI announced a $110B in new funding, with $30B from Nvidia, $30B from Softbank and $50B from Amazon. In a $100B multi-year deal, Meta will power its AI infrastructure with up to 6GW of AMD's GPUs. SambaNova and Intel ar... » read more

Blog Review: Feb. 25


Cadence's Mick Posner introduces the Foundational Chiplet System Architecture, a specification that aims to deliver a vendor and CPU-neutral architecture, common system partition guidelines, and a shared vocabulary and set of standards for system-level and interface definitions between chiplets. Synopsys' Scott Knowlton explains why LPDDR6 represents a big step forward in memory management c... » read more

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