tag: 2D materials

A Deionized Water-Based Large-Scale Transfer Process For 2D Materials Grown on Sapphire (AMO, RWTH, Aixtron)
By Technical Paper Link - 18 May, 2026 - Comments: 0

A new technical paper, "Water-based, large-scale transfer of 2D materials grown on sapphire substrates," was published by researchers at AMO GmbH, RWTH Aachen University, and AIXTRON SE. Abstract "Two-dimensional materials (2DMs) hold significant potential for future electronics, as demonstrated by high-performing devices for sensing, optics, and electronics. However, scalable growth tech... » read more

2D Semiconductors Inch Forward
By Katherine Derbyshire - 19 Mar, 2026 - Comments: 0

Key Takeaways: Diffusing oxygen into 2D materials can improve adhesion properties. Channel-last processes can preserve most of the traditional gate-all-around process flow. Dual-gate MoS2 FETs with graphene contacts take advantage of layer transfer methods. Transition metal dichalcogenides (TMDs) have come a long way since exfoliated flakes were the state of the art, but the... » read more

Nanoscale MoS₂-based Memristors Integrated into CMOS Microchips
By Technical Paper Link - 20 Feb, 2026 - Comments: 0

A new technical paper, "Integration of Low-Voltage Nanoscale MoS2 Memristors on CMOS Microchips" was published by RWTH Aachen and Forschungszentrum Jülich GmbH. Abstract "2D materials (2DMs) are gaining increased attention for applications such as advanced electronics and neuromorphic computing due to their excellent electrical properties. Among these 2DMs, molybdenum disulfide (MoS2) ha... » read more

Overview of Interface Dipole Engineering: Formation Mechanisms, Control Methods, And Emerging Applications (SNU, Sejong U.)
By Technical Paper Link - 06 Feb, 2026 - Comments: 0

Researchers at Seoul National University and Sejong University published "Interface dipole modulation for gate dielectrics in Field-Effect transistors: a review." Abstract "Interface dipole engineering has recently become a key technology in the fabrication of semiconductor FETs. This review comprehensively covers the principles, methods, and applications of interface dipoles in gate diel... » read more

300mm Fab-Compatible Integration Flow for Planar 2D FETs (imec, KU Leuven)
By Technical Paper Link - 04 Feb, 2026 - Comments: 0

Imec and KU Leuven researchers published "Integration and electrical evaluation of WS2 and MoS2 fets in a 300 mm pilot line." Abstract "2D materials have the potential to extend and augment the CMOS scaling roadmap. However, upscaling from lab-based demonstrators to 300 mm-compatible integration modules presents unique challenges. In this work, we address these challenges through ... » read more

Impact Of The Film Transfer And Grain Size On The Cu-barrier Properties Of 2D WS2 Films (NUS et al.)
By Technical Paper Link - 29 Jan, 2026 - Comments: 0

A new technical paper titled "Enhancing Cu-barrier properties of 2D-WS2 barriers: The role of grain size and surface passivation" was published by researchers at National University of Singapore, AIXTRON, IMiF and Applied Materials. Abstract "Two-dimensional (2D) films, such as tungsten disulfide (WS2), are being considered by the microelectronics industry as promising barrier and liner s... » read more

Minimizing Optical Loss While Enabling Efficient Phase Modulation in TMD-Based Devices (Nanyang Technological Univ., et al.)
By Technical Paper Link - 12 Jan, 2026 - Comments: 0

A new technical paper titled "Hybrid tungsten oxyselenide/graphene electrodes for near-lossless 2D semiconductor phase modulators" was published by researchers at Nanyang Technological University, CNRS-International-NTU-Thales Research Alliance (CINTRA), University of Chicago, University of Wisconsin-Madison, Chungnam National University, National Institute for Materials Science, MIT, and Singa... » read more

Thermal Scanning-Probe Lithography in vdW Heterostructures (Technical University of Denmark)
By Technical Paper Link - 06 Jan, 2026 - Comments: 0

A new technical paper titled "Gradient Electronic Landscapes in van der Waals Heterostructures" was published by researchers at Technical University of Denmark. Abstract Excerpt "Here, we use thermal scanning-probe lithography to produce smooth topographic landscapes in vdW heterostructures by patterning the thickness of the top hBN flake with nanometer precision." Find the technical p... » read more

Tunnel FETs: Surpassing the Energy Efficiency of Conventional MOSFETs (Sandia Labs)
By Technical Paper Link - 03 Dec, 2025 - Comments: 0

A new technical paper titled "Next-generation tunnel FETs: exploring material perspectives and areal tunneling configurations" was published by researchers at Sandia National Laboratories. Abstract "The end of Dennard scaling, which facilitated proportional increases in computing power without added energy costs until the mid-2000s, has underscored the urgent need for innovative semicondu... » read more

3D Imaging Buried Interfaces In Twisted Oxide Moirés (Cornell, SLAC, Stanford et al.)
By Technical Paper Link - 11 Nov, 2025 - Comments: 0

A new technical paper titled "Mind the Gap -- Imaging Buried Interfaces in Twisted Oxide Moirés" was published by researchers at Cornell University, SLAC National Accelerator Laboratory, Stanford University, USC, North Carolina State University, University of Chicago, Institute for Basic Science and POSTECH. Abstract "The ability to tune electronic structure in twisted stacks of layered, t... » read more

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