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Using More Germanium In Chips for Energy Efficiency & Achievable Clock Frequencies


A new technical paper titled "Composition Dependent Electrical Transport in Si1−xGex Nanosheets with Monolithic Single-Elementary Al Contacts" was published by researchers at TU Wien (Vienna University of Technology), Johannes Kepler University, CEA-LETI, and Swiss Federal Laboratories for Materials Science and Technology. Find the technical paper here. Published September 2022. Abstrac... » read more

Full Wafer Integration of Aggressively Scaled 2D-Based Logic Circuits (Imec)


A technical paper titled "Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits" was published by researchers at Imec. "The introduction of highly scaled 2D-based circuits for high-performance logic applications in production is projected to be implemented after the Si-sheet-based CFET devices. Here, a view on the requirements needed for full waf... » read more

What’s Different About Next-Gen Transistors


After nearly a decade and five major nodes, along with a slew of half-nodes, the semiconductor manufacturing industry will begin transitioning from finFETs to gate-all-around stacked nanosheet transistor architectures at the 3nm technology node. Relative to finFETs, nanosheet transistors deliver more drive current by increasing channel widths in the same circuit footprint. The gate-all-aroun... » read more

The High Price Of Smaller Features


The semiconductor industry’s push for higher numerical apertures is driven by the relationship between NA and critical dimension. As the NA goes up, the CD goes down: Where λ is the wavelength and k1 is a process coefficient. While 0.55 NA exposure systems will improve resolution, Larry Melvin, principal engineer at Synopsys, noted that smaller features always come with a process cos... » read more

Scaling Down To 2nm: Using Microwaves For Efficient & Stable Doping


A new technical paper titled "Efficient and stable activation by microwave annealing of nanosheet silicon doped with phosphorus above its solubility limit" was just published by researchers at National Taiwan University, Cornell University, TSMC, University of Valladolid, DSG Technologies, National Central University and National Yang Ming Chiao Tung University. A modified microwave was used... » read more

Big Changes In Architectures, Transistors, Materials


Chipmakers are gearing up for fundamental changes in architectures, materials, and basic structures like transistors and interconnects. The net result will be more process steps, increased complexity for each of those steps, and rising costs across the board. At the leading-edge, finFETs will run out of steam somewhere after the 3nm (30 angstrom) node. The three foundries still working at th... » read more

Nanosheet FETs Drive Changes In Metrology And Inspection


In the Moore’s Law world, it has become a truism that smaller nodes lead to larger problems. As fabs turn to nanosheet transistors, it is becoming increasingly challenging to detect line-edge roughness and other defects due to the depths and opacities of these and other multi-layered structures. As a result, metrology is taking even more of a hybrid approach, with some well-known tools moving... » read more

New Materials Open Door To New Devices


Integrating 2D materials into conventional semiconductor manufacturing processes may be one of the more radical changes in the chip industry’s history. While there is pain and suffering associated with the introduction of any new materials in semiconductor manufacturing, transition metal dichalcogenides (TMDs) support a variety of new device concepts, including BEOL transistors and single-... » read more

Synchrotron S-ray Diffraction-based Non-destructive Nanoscale Mapping of Si/SiGe Nanosheets for GAA structures


New research paper titled "Mapping of the mechanical response in Si/SiGe nanosheet device geometries" from researchers at IBM T.J. Watson Research Center and Brookhaven National Laboratory. Sponsored by U.S. DOE. Abstract "The performance of next-generation, nanoelectronic devices relies on a precise understanding of strain within the constituent materials. However, the increased flexibilit... » read more

Scalable Approach to Fabricate Memristor Arrays at Wafer-scale


New technical paper titled "Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing" from researchers at National University of Singapore and Institute of High Performance Computing, Singapore. Abstract "Realization of high-density and reliable resistive random access memories based on two-dimensional semiconductors is crucial toward their develop... » read more

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