tag: nanosheets

Challenges In Scaling Chips To 2nm And Below
By Ed Sperling - 30 Mar, 2026 - Comments: 0

Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

Channel-Last GAA NS Oxide FET (Stanford, TSMC, ETH Zurich et al.)
By Technical Paper Link - 03 Jan, 2026 - Comments: 0

A new technical paper titled "Channel-last gate-all-around nanosheet oxide semiconductor transistors" was published by researchers at Stanford University, TSMC, ETH Zurich, SLAC National Accelerator Laboratory, and Polish Academy of Sciences. Abstract "As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the t... » read more

Colloidal Coordination Nanosheets, And Their Use as Inks For Coating (Tokyo University of Science)
By Technical Paper Link - 11 Jul, 2025 - Comments: 0

A new technical paper titled "Rationally Engineered Heterometallic Metalladithiolene Coordination Nanosheets with Defined Atomic Arrangements" was published by researchers at Tokyo University of Science. Abstract "Coordination nanosheets are 2D polymers formed by coordination bonds between metal ions and planar organic molecules. They offer high molecular design freedom and unique electroni... » read more

Scalability of Nanosheet Oxide FETs for Monolithic 3-D Integration
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "High-Field Transport and Statistical Variability of Nanosheet Oxide Semiconductor FETs With Channel Length Scaling" was published by researchers at The University of Tokyo and Nara Institute of Science and Technology. Abstract "We have investigated the scaling potential of nanosheet oxide semiconductor FETs (NS OS FETs) for monolithic 3-D (M3D) integration in t... » read more

Powering CFETs From The Backside
By Katherine Derbyshire - 21 Mar, 2024 - Comments: 0

The first CMOS circuits to incorporate backside power connections are likely to be based on stacked nanosheet transistors, but further down the road, planners envision complementary transistors (CFETs) that vertically integrate stacked NFET and PFET devices. With at least twice the thickness of a nanosheet transistor, connecting CFETs to each other and to the rest of the circuit is likely to... » read more

Research Bits: Mar. 11
By Jesse Allen - 11 Mar, 2024 - Comments: 0

Ferroelectric nanosheets Engineers from the University of Sydney, RMIT University, University of New South Wales, and University of Technology Sydney created a liquid metal alloy of tin, zirconium, and hafnium. The alloy has a thin oxide layer crust that enables it to be used to harvest ultra-thin tin oxide nanosheets doped with hafnium zirconium oxide, which could then be 2D printed on a subs... » read more

SRAM Scaling Issues, And What Comes Next
By Karen Heyman - 15 Feb, 2024 - Comments: 0

The inability of SRAM to scale has challenged power and performance goals forcing the design ecosystem to come up with strategies that range from hardware innovations to re-thinking design layouts. At the same time, despite the age of its initial design and its current scaling limitations, SRAM has become the workhorse memory for AI. SRAM, and its slightly younger cousin DRAM, have always co... » read more

Investigating Subthreshold Current Suppression in ReS2 Nanosheet-Based FETs
By Technical Paper Link - 26 Nov, 2023 - Comments: 0

A technical paper titled “Subthreshold Current Suppression in ReS2 Nanosheet-Based Field-Effect Transistors at High Temperatures” was published by researchers at University of Salerno, Università degli studi del Sannio, and University of Exeter. Abstract: "Two-dimensional rhenium disulfide (ReS2), a member of the transition-metal dichalcogenide family, has received significant attention... » read more

Navigating the Metrology Maze For GAA FETs
By Gregory Haley - 08 Aug, 2023 - Comments: 1

The chip industry is pushing the boundaries of innovation with the evolution of finFETs to gate-all-around (GAA) nanosheet transistors at the 3nm node and beyond, but it also is adding significant new metrology challenges. GAA represents a significant advancement in transistor architecture, where the gate material fully encompasses the nanosheet channel. This approach allows for the vertical... » read more

Nanosheet GAAFETs: Compact Modeling (Politecnico di Torino)
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance” was published by researchers at Politecnico di Torino. Abstract: "NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as ... » read more

← Older posts

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy