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Gate-All-Around FET (GAA FET)

A transistor design with a gate is placed on all four sides of the channel.


As the fin width in a finFET approaches 5nm, channel width variations could cause undesirable variability and mobility loss. One promising transistor candidate — gate-all-around FET — could circumvent the problem. Considered the ultimate CMOS device in terms of electrostatics, gate-all-around is a device in which a gate is placed on all four sides of the channel. It’s basically a silicon nanowire with a gate going around it. In some cases, the gate-all-around FET could have InGaAs or other III-V materials in the channels.

The approach allows for the vertical stacking of planar channels, leading to a notable increase in the effective channel width. By stacking these planar channels vertically, the effective channel width is increased, resulting in increased device drive current capability with less leakage, reduced power consumption, and enhanced performance.

Fig. 1: Planar transistors vs. finFETs vs. gate-all-around Source: Lam Research
Fig. 1: Planar transistors vs. finFETs vs. gate-all-around Source: Lam Research

Nanosheet GAA

Horizontally stacked nanosheets are emerging as an industry consensus for 5nm, according to IBM. These devices start with alternating layers of silicon and silicon germanium (SiGe), patterned into pillars.

Creating the initial Si/SiGe heterostructure is straightforward, and pillar patterning is similar to fin fabrication. The next several steps are unique to nanosheet transistors, though. An indentation in the SiGe layers makes room for an inner spacer between the source/drain, which will eventually be deposited next to the pillar and the space where the gate will be. This spacer defines the gate width. Then, once the inner spacers are in place, a channel release etch removes the SiGe. ALD deposits the gate dielectric and metal into the spaces between the silicon nanosheets.

To minimize lattice distortion and other defects, the germanium content of the SiGe layers should be as low as possible. Etch selectivity increases with Ge content, though, and erosion of the silicon layers during either the inner spacer indentation or the channel release etch will affect channel thickness and therefore threshold voltage.

Nanowire GAA

In the lab, several entities are working on nanowire gate-all-around FET. For example, IBM described a gate-all-around silicon nanowire FET, which achieved a nanowire pitch of 30nm and a scaled gate pitch of 60nm. The device had an effective nanowire dimension of 12.8nm.

In IBM’s gate-all-around fabrication process, two landing pads are formed on a substrate. The nanowires are formed and suspended horizontally on the landing pads. Then, vertical gates are patterned over the suspended nanowires. In doing so, multiple gates are formed over a common suspended region.

A spacer is formed. Then, the silicon nanowires are cut outside the gate region, according to IBM. In-situ doped silicon epitaxy is then grown from the exposed cross sections of the silicon nanowires at the edge of the spacer, according to IBM. Conventional self-aligned, nickel-based silicide contacts and copper interconnects were used to complete the device.

There are other versions of gate-all-around. For example, the National University of Singapore, Soitec and Leti recently described a Ge gate-all-around nanowire PFET. With a wire width of 3.5nm, the device was integrated with a phase change material, Ge2Sb2Te5 (GST), as a liner stressor, thereby boosting the mobility.

In addition, National Cheng Kung University has developed a stacked silicon nanowire MOSFET. The MOSFET, which can be classified as a gate-all-around FET, also makes use of a silicon-on-insulator (SOI) substrate. A flexible doping scheme has also been devised to enable high-performance and low-operating power designs with the technology.

Using silicon/silicon-germanium superlattice epitaxy and an in-situ doping process for stacked wires, researchers have developed a stacked, four-wire gate-all-around FET. The gate-length for the device is 10nm. Both the channel width and the height are 10nm, based on an electrostatic scale length of 3.3nm.

“Threshold voltage doping (schemes) for stacked wires is far different than for conventional approach, especially when multiple layers of transistors are integrated on the same substrate,” according to a paper from the university. “Leaving the channel undoped has an advantage in mobility and is expected to relieve the issue of random dopant fluctuation, but it does not meet the need for multi-Vt design being commonly used in SoC applications. Instead, different gate work functions (or gate materials) will be needed for different Vt’s, and hence, such undoped approach would be even more complicated.”

Researchers have implemented a different approach. “During epitaxy process, the in-situ doped channel is implemented for each of the stacked wires,” according to researchers. “Doped stacked-GAA MOSFETs provide flexible options for Vt adjustment.”


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